6657 initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec so a delay of an additional 16 μs is required before a rising edge of POR
During the 16 μs ,RBL take over the initialization ? i though the RBL execute after the POR and RESETFULL signal released , so why a delay of an additional 16 μs is required before a rising edge of POR
Can you describe the initialization step clearly
