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Bitstream interface with AM335x

Prad1
Genius 3825 points
Other Parts Discussed in Thread: DAC1280, AM3352

Hi,

We need some advice about connecting AM3352 and DAC1280.
The DAC1280 has a Bitstream interface.

Below is the DAC1280 System Block Diagram, it needs a clock source(4.096MHz)
and a 256Khz bitstream source from the Controller(AM335x).


We need to know which peripheral could be used in this case.
In case of GPIO it may put more load on the CPU.
Please let me know whether using a PWM module or McASP could be a
best possible solution.

Best Regards.
Prad

  • 0
    TI__Guru**** 393215 points
    Hi Prad,
     
    I suppose the McASP will be best suited to handle this, but I don't think there is any ready to use software implementation for this, so the customer will have to write their own.
  • 0 in reply to Biser Gatchev-XID
    Genius 3825 points

    Hi Biser,

    Thank you.

    Please excuse me for so many questions.
    I am new to McASP and little bit confused which pins should be used in this case.
    The DAC1280 requires a clock source 4.096MHz and a bitstream source TDATA(256kHz).

    According to the TRM manual I believe we could control the
    Transmit clock(McASPx_ACLKX),Frame sync(McASPx_FSX) and Data(McASPx_AXR0) pins.
    Please let me know if the below connection is a proper way to use McASP.


    Regarding the clock source the "Table 22-3. McASP Clock Signals" in TRM
    mentions Functional clock (auxclk) is derived from CLK_M_OSC =26 MHz.
    Is this clock derived from the external crystal? and is this a internal clock?
    And the DAC needs a Bitstream Source TDATA(@256kHz), would this be possbile from the McASP?


    Best Regards
    Prad

  • 0 in reply to Prad1
    TI__Guru**** 393215 points
    Hi Prad,
     
    Bitstream data can be transmitted from any of the AXR[3:0] pins. You will need an external 4.096MHz oscillator to provide the reference clock for the DAC and the McASP (input on pin AHCLKX). This will be divided by 16 inside the McASP to produce the 256kHz bit clock. The DAC SYNC input will have to be driven by GPIO I think, because the AFSX will not be able to provide the signal required by the DAC (this is Frame Synchrobization for audio formats).
  • 0 in reply to Biser Gatchev-XID
    Genius 3825 points

    Hi Biser,

    Thank you so much.

    Just in case we would like to know that
    is it necessary to connect external 4.096MHz clock,
    isn't it possible to use the inbuilt McASP clock?

    And we are confused about how to generate the "SYNC" signal to the DAC1280.

    According to the Datasheet of DAC1280, it says
    When SYNC is taken high, the DAC resumes sampling TDATA on the sixth rising
    CLK edge after SYNC is high.

    So I think the data from the McASP should be delayed at the beginning for five clock 
    cycles so that the DAC samples the TDATA Properly.
    Is there any options in the McASP to delay the data for few cycles.


    Best Regards.
    Prad

  • 0 in reply to Prad1
    TI__Guru**** 393215 points
    You will not be able to generate the requred 4.096MHz frequency internally. As for the SYNC signal I don't think that McASP data can be delayed more than 2 bit clock cycles if the McASP Frame Sync is used. This would transfer to 0, 16 or 32 clock cycles of the 4.096MHz clock. You should check whether this SYNC signal is really needed. I cannot say because I don't have expertise on this DAC. You can ask on: http://e2e.ti.com/support/data_converters/precision_data_converters/f/73.aspx