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[OMAP3530] Inclusive and Exclusive Cache

hdp
Intellectual 330 points
Other Parts Discussed in Thread: OMAP3530

Is the OMAP3530 cache structure Inclusive or Exclusive? Is this something that is configurable for both the L1 and L2?

I ran a simulation with my code on the DM6437 simulator and inclusive simulation results is similar to the on target code execution results. I thought that the OMAP3530 cache is exclusive?

 

thanks

 

  • 0
    TI__Mastermind 41665 points

    Assuming you mean the C64x+ DSP core on the OMAP3 (based on your DM6437 mention) the cache is inclusive, that is data cached in L1 will also be present in L2. This is not configurable, it is a fundamental property of the C6x cache architecture. For a good description of how the cache operates on the C64x+ you may want to look at SPRU862, in particular section 1.8.4 discusses the L2 cache and how it interacts with the L1 caches. Though it does not call the cache inclusive explicitly, it is implied by how the L1 cache must first check if the object is in L2 and that L2 must bring in the object to itself and then pass it on to L1.