• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Subscribers 97 subscribers
  • Views 923 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LPDDR Timing issue

Harsha Kiran
Intellectual 545 points
Other Parts Discussed in Thread: AM3358

Hi Everyone,

I am working on a AM3358 custom board and we are using LpDDR SDRAM on it..

We have a problem with the data read from the LPDDR SDRAM address. I am using a BDI3000 Jtag debugger to do my memory tests. 

These are the observations we made..

1) When i write 0xffffffff at 0x80200000 address, i see ffffffff written at the address. When i read back the data at the address, i get the same value back. even if i read the data multiple times i read the same data

UFLOW>md 0x80200000
80200000 : ffffffff ffffffff ffffffff ffffffff ................
80200010 : ffffffff ffffffff ffffffff ffffffff ................
80200020 : ffffffff ffffffff ffffffff ffffffff ................
80200030 : ffffffff ffffffff ffffffff ffffffff ................

2) But, When i write 0x00000000 at 0x80200000, i see that some of the bit values are changing everytime i read.

UFLOW>mm 0x80200000 0x00000000 16
UFLOW>md 0x80200000
80200000 : ff04ff04      00006004 00006004 00002004 .....`...`... ..
80200010 : 00000000 00006004 00000004 00006004 .....`.......`..
80200020 : 00000000 00006004 00000004 00000004 .....`..........
80200030 : 00000000 00000004 00000004 00006004 .............`..

3) We performed some memory tests writing some patterns and identified only some bits are inconsistent everytime

These are the register values we are using..

config_ddr(200, MT46H128M16LF_IOCTRL_VALUE, &lpddr_data,
&lpddr_cmd_ctrl_data, &lpddr_emif_reg_data, 0);

 Clock rate = 200

we got the emif registers from the AM335x_EMIF_config tool according to the RAM timings..

/*Config tool*/

#define MT46H128M16LF_EMIF_READ_LATENCY 0x04

#define MT46H128M16LF_EMIF_TIM1 0x04447289
#define MT46H128M16LF_EMIF_TIM2 0x10160580
#define MT46H128M16LF_EMIF_TIM3 0x000000E7
#define MT46H128M16LF_EMIF_SDCFG 0x20044EA3
#define MT46H128M16LF_EMIF_SDREF 0x00000618
#define MT46H128M16LF_DLL_LOCK_DIFF 0x0

/*ratio spreadsheet
*
/

#define MT46H128M16LF_INVERT_CLKOUT 0x0
#define MT46H128M16LF_PHY_RD_DQS 0x40
#define MT46H128M16LF_PHY_FIFO_WE 0x200
#define MT46H128M16LF_PHY_WR_DQS 0x1
#define MT46H128M16LF_PHY_WR_DATA 0x40
#define MT46H128M16LF_RATIO 0x80
#define MT46H128M16LF_PHY_RANK0_DELAY 0x01
#define MT46H128M16LF_PHY_WRLVL 0x0
#define MT46H128M16LF_PHY_GATELVL 0x0

#define MT46H128M16LF_IOCTRL_VALUE 0x18B

The RAM is on full drive strength.. are there any registers that should be modified for the LpDDR??

our trace lengths are 

Trace Length (inches)
Byte 0 Byte 1
DDR_CK trace 1.15361 1.15361
DDR_DQSx trace 1.04342 1.04074
Appreciate your time.
Thanks,
Harsha
  • 0
    TI__Intellectual 1585 points

    I have a working LPDDR1 board (an early EVM), and I can share a few differences I see:

    PHY_FIFO_WE 0x110
    EMIF_SDREF 0x61a

    I can't see the full value for EMIF_SDCFG, but here are some of the defined fields:

    REG_SDRAM_DRIVE 0x1
    REG_NARROW_MODE 0x1
    REG_CL 0x3
    REG_ROWSIZE 0x5
    REG_IBANK 0x2
    REG_PAGESIZE 0x2
    (remaining fields 0x0) 

  • 0 in reply to Greg Guyotte
    Intellectual 545 points

    Hi Thank you for the reply...

    EMIF_SDREF i have calculated as 200*7.8 = 0x618

    and for EMIF_SDCFG, i used..

    LPDDR: 001 00 000 0 00 0 10 00 01 0011 101 010 0 010 CAS 3= 0x20004EA2

    ie pagesize 3 (2048) for 11 address bits

    bank 2

    rowsize 5

    CL = 3

    narrowmode =1

    sdramdrive=0 for full drive

    and sdram_type=1...is ur RAM ddr1 or lpddr??

    what clock are you using?? and what were the trace lengths??

    Thanks,

    harsha

  • 0 in reply to Harsha Kiran
    Intellectual 545 points


    sorry it is

    LPDDR: 001 00 000 0 00 0 10 00 01 0011 101 010 0 011 CAS 3= 0x20004EA3

  • 0 in reply to Harsha Kiran
    TI__Intellectual 1585 points

    My RAM is LPDDR1, 200MHz clock.  No idea about trace lengths...I'm using the TI AM335x EVM rev 1.0A.

    Suggest you try sdramdrive=1.

  • 0 in reply to Greg Guyotte
    Intellectual 545 points

    Hi Greg,

    I have tried the values but the results got even bad. These are the values i am using...

    #define MT46H128M16LF_EMIF_READ_LATENCY 0x04

    #define MT46H128M16LF_EMIF_TIM1 0x08869319
    #define MT46H128M16LF_EMIF_TIM2 0x10170581
    #define MT46H128M16LF_EMIF_TIM3 0x000000F8
    #define MT46H128M16LF_EMIF_SDCFG 0x84EA2
    #define MT46H128M16LF_EMIF_SDREF 0x0000061A
    #define MT46H128M16LF_DLL_LOCK_DIFF 0x0

    /*ratio spreadsheet
    *
    * remove glvl, wlrl */

    #define MT46H128M16LF_INVERT_CLKOUT 0x0
    #define MT46H128M16LF_PHY_RD_DQS 0x40
    #define MT46H128M16LF_PHY_FIFO_WE 0x110
    #define MT46H128M16LF_PHY_WR_DQS 0x1
    #define MT46H128M16LF_PHY_WR_DATA 0x40
    #define MT46H128M16LF_RATIO 0x80
    #define MT46H128M16LF_PHY_RANK0_DELAY 0x01
    #define MT46H128M16LF_PHY_WRLVL 0x0
    #define MT46H128M16LF_PHY_GATELVL 0x0

    #define MT46H128M16LF_IOCTRL_VALUE 0x18B

    I am using the MT46H128M16LF 1GB with 2048 page size and 11 address lines, 14 data lines LPDDR SDRAM 

    Thanks,

    Harsha

  • 0 in reply to Harsha Kiran
    TI__Intellectual 1585 points

    Your TIM1/TIM2/TIM3 values changed....from my information, the original values you had matched mine.

  • 0 in reply to Greg Guyotte
    Intellectual 545 points

    Hi greg,

    Thanks for the reply..

    Here are the latest values after we made some changes. we have not seen any significant changes in the results.

    /* Config tool*/
    #define MT46H128M16LF_EMIF_READ_LATENCY 0x04
    #define MT46H128M16LF_EMIF_TIM1 0x04447289
    #define MT46H128M16LF_EMIF_TIM2 0x10160580
    #define MT46H128M16LF_EMIF_TIM3 0x000000E7
    #define MT46H128M16LF_EMIF_SDCFG 0x20044EA2
    #define MT46H128M16LF_EMIF_SDREF 0x0000061A
    #define MT46H128M16LF_DLL_LOCK_DIFF 0x0
    /*ratio spreadsheet*/
    #define MT46H128M16LF_INVERT_CLKOUT 0x0
    #define MT46H128M16LF_PHY_RD_DQS 0x40
    #define MT46H128M16LF_PHY_FIFO_WE 0x110
    #define MT46H128M16LF_PHY_WR_DQS 0x1
    #define MT46H128M16LF_PHY_WR_DATA 0x40
    #define MT46H128M16LF_RATIO 0x80
    #define MT46H128M16LF_PHY_RANK0_DELAY 0x01
    #define MT46H128M16LF_PHY_WRLVL 0x0
    #define MT46H128M16LF_PHY_GATELVL 0x0

    #define MT46H128M16LF_IOCTRL_VALUE 0x18B

    Here are some observations when writing 0x00000000 to continuous 64 locations and when read, i get the below results..and they change on every read

    UFLOW>md 0x80200000
    80200000 : ff04ff0f 0004f00f 0004f00f 0004f00f ................
    80200010 : 0004f00f 0004f00f 0004f00f 0004f00f ................
    80200020 : 0000f00f 0000f00f 0000f00f 0000f00f ................
    80200030 : 0000f00f 0000f00f 0000f00f 0000f00f ................
    80200040 : 0000f00f 0000f00f 0000f00f 0000f00f ................
    80200050 : 0000f00f 0000f00f 0000f00f 0000f00f ................
    80200060 : 0000f00f 0000f00f 0000f00f 0000f00f ................
    80200070 : 0000f00f 0000f00f 0000f00f 0000f00f ................
    80200080 : 0000f00f 0000f00f 0000f00f 0000f00f ................
    80200090 : 0000f00f 0000f00f 0000f00f 0000f00f ................
    802000a0 : 0000f00f 0000f00f 0000f00f 0000f00f ................
    802000b0 : 0000f00f 0000f00f 0000f00f 0000f00f ................
    802000c0 : 0000f00f 0000f00f 0000f00f 0000f00f ................
    802000d0 : 0000f00f 0000f00f 0000f00f 0000f00f ................
    802000e0 : 0000f00f 0000f00f 0000f00f 0000f00f ................
    802000f0 : 0000f00f 0000f00f 0000f00f 0000f00f ................

    and we get the below results if we write 0xffffffff

    80200000 : ffffffff ffffffff ffffffff ffffffff ................
    80200010 : ffffffff ffffffff ffffffff ffffffff ................
    80200020 : ffffffff ffffffff ffffffff ffffffff ................
    80200030 : ffffffff ffffffff ffffffff ffffffff ................
    80200040 : ffffffff ffffffff ffffffff ffffffff ................
    80200050 : ffffffff ffffffff ffffffff ffffffff ................
    80200060 : ffffffff ffffffff ffffffff ffffffff ................
    80200070 : ffffffff ffffffff ffffffff ffffffff ................
    80200080 : ffffffff ffffffff ffffffff ffffffff ................
    80200090 : ffffffff ffffffff ffffffff ffffffff ................
    802000a0 : ffffffff ffffffff ffffffff ffffffff ................
    802000b0 : ffffffff ffffffff ffffffff ffffffff ................
    802000c0 : ffffffff ffffffff ffffffff ffffffff ................
    802000d0 : ffffffff ffffffff ffffffff ffffffff ................
    802000e0 : ffffffff ffffffff ffffffff ffffffff ................
    802000f0 : ffffffff ffffffff ffffffff ffffffff ................

    here the values remain same after every read

    Thanks,

    harsha

  • 0 in reply to Harsha Kiran
    Intellectual 545 points

    Hi!

    We still have trouble getting the LPDDR to work. We are analyzing all the root causes. could you please let me know how can i figure out if the issue is with software or hardware.

    1) Can trace lengths of the DDR_DQ[0-15] signals can have effect on bit syncronization?? we observed that the trace lengths of all the data lengths from the processor to the SDRAM are different.

    Appreciate your time

    Thanks,

    Harsha

  • 0 in reply to Harsha Kiran
    Intellectual 545 points

    Hi!

    We have finally made the LpDDR working. The timing vales generated from the ratio spread sheet and the EMIF_config tool are correct. 

    The mistake was in writing the correct bit on ddrioctrl . we were just writing 0x1 to the register.

    writel((0x01<<28), &ddrctrl->ddrioctrl); made it work!

    Thanks for all the help!

    -Harsha