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USB mass storage problem

____-__-__
Intellectual 780 points
Other Parts Discussed in Thread: OMAPL138

Hi,

     I'm working in a project that should realize a usb mass storage device usingOMAPL138 usb2.0 module. I've designed two  kind of board with the same schematic but different PCB. One of them provides 20MHz clock to OMAPL138, and the other one provides 40MHz. The former works well whether writing or reading a file from the mass storage, but the latter can only read files.

    I  used CPU for transforming but  CPPI DMA, and found that every time the PC send a packet of data larger than 512 bytes( the FIFO size), the CPU can only get 512 bytes from the FIFO, then no interrupt occurred. Dose it mean i have to use CPPI DMA when the packet size may be larger than the FIFO size? And what confused is why one of my board with the same schematic and programming(of course the usb2.0 controller was configured for different clock frequency) can works well.

Thanks,

Huang.

) 

  • 0
    TI__Guru* 81335 points

    Hi Huang,

    Thanks for the post.

    Pleaes ensure to enable two interrupts i.e. one for short packets and one for "received data equal to RXMAXP".

    CPPI DMA:

    Reference: TRM-SPRUH77A, Page No: 1646.

    In Transparent mode, DMA interrupt is generated whenever a DMA packet is transferred.

    In RNDIS mode, Multiple USB packets will be transferred and DMA interrupt is generated only at the end of the complete reception of DMA transfer.

    For Rx transparent mode, RXMAXP must be a valid USB EP size.

    • FS: 8, 16, 32, 64, and 1023

    • HS: 64, 128, 512, and 1024

    The CPPI packet size should be equal to RXMAXP.

    If the received data is equal to RXMAXP, then an interrupt will be generated. If the received data is less than RXMAXP, this is a short packet, and an interrupt will be generated.

    Please use the latest Starterware package from below link.(01.10.04.01)

    http://processors.wiki.ti.com/index.php/StarterWare

  • 0 in reply to Raja
    TI__Guru**** 176281 points

    Huang

    Just to confrim, USB0REF_FREQ of CFGCHIP2 register is set to either 8h or 9h for the different input frequency?

    Thanks 

    David

  • 0 in reply to David (ASIC) Liu
    Intellectual 780 points
    hi David, thanks for reply, i have already checked my USB0REF_FREQ, and both the two board is set right. yours huang
  • 0 in reply to Raja
    Intellectual 780 points
    Hi Rajasekaran, Thanks a lot for your reply. Now i do want to receive data using cppidma. I learned the file and the startware, but i cannot find any information about the dma interrupt in the file. The startware uses some registers that be addressed at a offset of 0x3200 seems to have something to do with the dma interrupt, but i cannot find the register in the file.Can you tell me whether these registers exist or not? And where can i find some information about the cppidma interrupt? Thanks, Yours Huang.
  • 0 in reply to Raja
    Intellectual 780 points
    Hi Rajasekaran, Thanks a lot for your reply. Now i do want to receive data using cppidma. I learned the file and the startware, but i cannot find any information about the dma interrupt in the file. The startware uses some registers that be addressed at a offset of 0x3200 seems to have something to do with the dma interrupt, but i cannot find the register in the file.Can you tell me whether these registers exist or not? And where can i find some information about the cppidma interrupt? Thanks, Yours Huang.
  • 0 in reply to ____-__-__
    TI__Guru**** 176281 points

    Huang

    Thanks for confirming USB0REF_FREQ setting. When you say same schematic, but different PCB, besides the input clock difference, are there any other differences between the two designs? For the 20MHz design, is it possible to change the input clock to 40MHz and see if it is able to read/write data?

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Intellectual 780 points
    David I tried to change the input clock to 20MH, but the problem has nothing changed. Then i used cppi41 for transmitting, and set the rx mode as RNDIS. I can get the data sent by pc correctly when the packet length is less than 0x400, which is twice of the endpoint fifo length, but lost the rest of data when the packet length be longer. I learned from the user guide that cppi41 should link the free descriptor submitted to SubmitQ together when the whole packet be received, and send a pointer of host packet to the rx completionQ, but i found the nextpointer that belongs to the host packet descriptor is always null. So where can i get the other buffer descritor? And how many times the rx completionQ should be read in a rx interrupt routine?Are those free descriptor linked by cppi41automaticly? At last, what role the linkram plays of? I got no idea with it at all. Thank you very much. Huang