Interrupt service routines(ISR)

sureshkumar said:

1 . I wanted to use ISR in my dsp side application, wher should i get the sample programs which includes ISR.

Typically within a DSP side application you would be using DSP/BIOS, which makes configuration of interrupts easier since you can do most of the work through the GUI BIOS configuration tool, there is some discussion on interrupts (HWI) in section 4.2 of SPRU303. As to an example I am not sure that there are any good ones out there, primarily because the DSP on the OMAP3 is generally used as a peripheral of the ARM as opposed to a processor on its own, so normally all of the interrupt signals in the system end up going to the ARM which handles all the peripherals through Linux device drivers, you may be able to port an example from a prior device however.

sureshkumar said:

2 My application needs a ISR such a way that "after performing the given task it should notify the dsp or perform the other operation(DMA) by checking the ISR flag"  

I am not sure exactly what you mean, are you now talking from the ARM perspective? Typically an ISR is run after an event generated by some hardware peripheral, such as a serial port, GPIO, timer, DMA, etc, than within the ISR you would decide what to do, such as perform another DMA operation.

sureshkumar said:

3.how many ISRs can be supported in OMAP3530 in general?

Note I am assuming this is entirely from the DSP perspective. By putting in switch case logic in an ISR you can handle a virtually unlimited number of possible outcomes, however in the case of the C64x+ it actually handles just 14 individual unique CPU interrupts including Reset and NMI, this gives you effectively 12 unique ISRs. To expand upon this, the C64x+ has an interrupt controller (INTC) that allows you to select from 128 source events to be routed into the unique CPU interrupts, it also supports combining events to support more than 14 interrupt sources. You can read more on the INTC module in chapter 7 of SPRU871.

I'm trying to get interrupts working on the DSP side too, and I'm stuck so I wanted to continue the discussion thread.  I'm working without DSP/BIOS for some hardware debugging.  I want to trigger on the falling edge of an input to GPIO_98.

Here are my steps:

(1) I configure Pin C23 (cam_fld) for Mode 4 (gpio_98) in CONTROL_PADCONF_CAM_FLD.  This gets my signal into the pin.

(2) I write CSL_INTC_EVENTID_GPIOBNK4 (76) to INTMUX1.  I expect this configures INTC interrupt 4 to respond to the GPIO 4 module.

(3) I write 0x4 to GPIO4_FALLINGDETECT.  I expect this will select a falling edge for GPIO_98.

(4) I reset interrupts in the C64 by writing 0 to GIE bit in CSR, write 0 to IER, and 0xFFFFFFFF to ICR.

(5) I write 0x12 to IER to enable interrupt 4 and NMI in the C64 INTC.

(6) I enable global interrupts by writing 1 to GIE bit in CSR.

Here's where the strangeness begins.

I write 0x4 to GPIO4_IRQENABLE2 to enable GPIO_98 as an interrupt.  If I poll GPIO4_IRQSTATUS2, I see bit 2 go high based on my input signal.  This makes me think the edge detection is working correctly, but the INTC never interrupts.  (I never see a change in the IFR register.)

I can clear GPIO4_IRQSTATUS2 and when my interrupt signal goes low (active) again on GPIO_98, then the GPIO4_IRQSTATUS2 bit 2 goes high again.  So I feel like the GPIO module is definitely seeing the edge, but this input is not triggering the INTC.

I'm setting up the interrupt vectors in assembly based on an example from CCS.  If this was set up wrong, I still expect to see something happen when an interrupt occurs (maybe a crash).

Has anyone been successful interrupting from a GPIO pin on the C64 side without DSP/BIOS?  I'm wondering if I'm missing a step somewhere.  Any thoughts/feedback is appreciated!

For my debug environment, I'm using an XDS560R emulator to step through and watch the Core registers and memory-mapped registers in CCS.  I'm scouring SPRU871, SPRUFA3, and SPRUFD5 for more clues.

I just discovered the gpio_interrupt project in CSL_3x_Reg_Layer_Examples.  I'm going to try this technique with DSP/BIOS instead of the 100% register level approach.