DDR3 and EMIF question on OMAP5432

Hello,

OMAP5432 chip supports up to 8 GB of dual channel DDR3 memory, but to achieve this you should use both EMIFs.

You cannot connect 2*4GB DDR3 to one EMIF in order to achieve 8GB DDR3 memory. 

Best Regards,

Yordan.

Hello Yordan,

I have a similar question on EMIF of OMAP5432.

From the datasheet, I understand that OMAP5432 has two EMIFs for total of 8GB memory. I don't need to use 8GB on application. My question is can I just use one EMIF to support 1GB (with 2 pcs of 4Gb chip) or 2GB (with 2 pcs of 8Gb chip) memory and how to do it?

Thanks,

TK

Hello, 

Yyou can achieve this.

From TRM we know that each emif has 2 channels. On each channel you can connect two ddr chips.

For example the reference design (OMAP5432 uEVM) is configured the following way: two 512MB DDR3 chips are connected to channel1 & channel2 of emif,  giving a total of 2 GB DRAM memory; you can refer to oma5 uevm system reference manual (http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=swcu130&fileType=pdf).

See part of the boot log of OMAP5432 uEVM bellow :

CPU  : OMAP5432 ES2.0
Board: OMAP5430 EVM
I2C:   ready
DRAM:  2 GiB
WARNING: Caches not enabled                                                    

You can connect two ddr to each channel of EMIF 1 for example, but after that your software should use both CS0 & CS1 of EMIF1.

Best Regards,

Yordan

Hello Yordan,

Thanks for quick response but I guess you misunderstand my question.

I do have the OMAP5432 EVM on hand. It has 4 DDR3 chips connected to 2 EMIFs as you mentioned. What I want to do is to use just one EMIF with 2 DDR3 chips for a total of 1GB on my design.

Is it possible and how to do it (software and hardware) ?

Best regards,

Tien-Kuen

Hello,

Yes you can connect 2DDR chips to only one memory controller (EMIF1). See figure bellow:

This use case is described in OMAP5430 TRM, Chapter 16 Memory Subsystem, Section 16.2.4.2.1 Case 1: Use of One Memory Controller.

For the electrical characteristics & PCB guidelines you should consult OMAP5432 Data Manual.

Best Regards,
Yordan

Hello Yordan,

Thanks for the answer but I can not find omap5430 TRM, seems omap5432 is the only product of omap5 family.

http://www.ti.com/lsds/ti/omap-applications-processors/omap-5-processors-products.page?paramCriteria=no

and it is in chapter 15 of omap5432 TRM.

Does TI develope the u-boot/linux by 'define' for using 2/4 DRAM chips? If not, could you direct me which file in the u-boot/linux source tree should be modified for the purpose?

Best regards,

Tien-Kuen

Hello Tien-Kuen, 

I apologize for the delayed response.

OMAP5430 TRM is actually called OMAP543x Technical Reference Manual (OMAP5432 device is included as an appendix, which highlights the differences in the various soc modules).

TRM link is:  http://www.ti.com/lit/ug/swpu249y/swpu249y.pdf

Official kernel releases are tuned for the TI reference platforms (in your case OMAP5432 uEVM); Therefore I cannot guarantee that GLSDK or Android kernels will work without modification on your custom board.

When changing the ddr chips you need to modify the u-boot emif drivers: emif-common.c & emif.c.

I think that the ddr register settings regarding timings, chip & chip geometry are already included in TI u-boot (but double check it anyway).

What you should consider is the LISA_MAP configurations. Currently the u-boot & kernel are configured to use both EMIFs and you are planning to use only one. For information regarding LISA_MAP settings please consult DMM chapter in device TRM.

Best Regards,

Yordan