Configuring CS7 of the OMAP

Vijay

Other Parts Discussed in Thread: AM3703

We are facing an issue which we are not sure if it related to our bug or related to Omap chip.

We are configuring the CS7 to be used as 16bit bus with un multiplexed mode.

The signal time that we would like to get for the CS is as follow -------|__50ns_____|----100ns------|__50ns_____|---------

When we are running writing sequence, we are getting it as above. At reading sequence, the 100ns increase to 200ns and we don’t know why.

Can you help us to fine what the problem is? (OMAP issue or software issue).

over 16 years ago

0 BrandonAzbell over 16 years ago

TI__Guru 64540 points

If you could provide the register settings for the CS7 configuration, this would be helpful. Also, please indicate which OMAP device part number you are working with.

Just a clarifying question, is the 100ns portion of the CS7 waveform meant to indicate CS7 at a logic high?

I want to make sure I interpret the waveform correctly. Here is my assumption:

CS7 high to low transition.
50ns low
100ns ?
50ns low
CS7 low to high transition

0 Vijay over 16 years ago in reply to BrandonAzbell

Intellectual 680 points

Hi Brandon,

Thanks for the reply. Below is the an excerpt of the c code that configures the CS7.The code setting for CS7 is not the exactly time setting that we achieved with read/write sequence..

#define        GPMC_CLK            150 //150MHZ
    #define     GPMC_CLK_PERIOD        (1000000/GPMC_CLK) // pico sec

    #define     RD_CYCLE_TIME_VAL       (((160/*ns*/ * 1000)/GPMC_CLK_PERIOD)             & 0x1F)
    #define     WR_CYCLE_TIME_VAL        (((160/*ns*/ * 1000)/GPMC_CLK_PERIOD)             & 0x1F)
    #define     CS_ONTIME_VAL            (((100/*ns*/ * 1000)/GPMC_CLK_PERIOD)             & 0x0F)
    #define     CS_RD_OFFTIME_VAL        ((CS_ONTIME_VAL + (50/*ns*/ * 1000)/GPMC_CLK_PERIOD) & 0x1F)
    #define     CS_WR_OFFTIME_VAL        CS_RD_OFFTIME_VAL
    #define     CS_OFFTIME_VAL          CS_RD_OFFTIME_VAL
    #define     OE_ONTIME_VAL            ((CS_ONTIME_VAL + (10/*ns*/ * 1000)/GPMC_CLK_PERIOD) & 0x0F)
    #define     OE_OFFTIME_VAL            ((CS_OFFTIME_VAL - (10/*ns*/ * 1000)/GPMC_CLK_PERIOD) & 0x1F)
    #define        WR_ONTIME_VAL            OE_ONTIME_VAL
    #define        WR_OFFTIME_VAL            OE_OFFTIME_VAL
    #define     RD_ACCESS_TIME_VAL        (((CS_ONTIME_VAL + (10/*ns*/ * 1000)/GPMC_CLK_PERIOD) -1) & 0x1F)
    #define     WR_ACCESS_TIME_VAL        RD_ACCESS_TIME_VAL

    #define     RD_CYCLE_TIME        (RD_CYCLE_TIME_VAL << 0)
    #define     WR_CYCLE_TIME        (WR_CYCLE_TIME_VAL << 8)
    #define     CS_ONTIME            (CS_ONTIME_VAL      << 0)
    #define     CS_RD_OFFTIME        (CS_RD_OFFTIME_VAL << 8)
    #define     CS_WR_OFFTIME        (CS_WR_OFFTIME_VAL << 16)
    #define     OE_ONTIME            (OE_ONTIME_VAL      << 0)
    #define     OE_OFFTIME            (OE_OFFTIME_VAL     << 8)
    #define        WR_ONTIME            (OE_ONTIME_VAL      << 16)
    #define        WR_OFFTIME            (OE_OFFTIME_VAL     << 24)
    #define     RD_ACCESS_TIME        (RD_ACCESS_TIME_VAL << 16)
    #define     WR_ACCESS_TIME        (RD_ACCESS_TIME_VAL << 24)

    # define FPGA_GPMC_CONFIG1        0x01801000 // 0x00C01000
    # define FPGA_GPMC_CONFIG2        (CS_WR_OFFTIME | CS_RD_OFFTIME | CS_ONTIME)                  // 0x00101000
    # define FPGA_GPMC_CONFIG3        0x00020201
    # define FPGA_GPMC_CONFIG4        (OE_ONTIME | OE_OFFTIME | WR_ONTIME | WR_OFFTIME)            // 0x10031003
    # define FPGA_GPMC_CONFIG5        (RD_CYCLE_TIME | WR_CYCLE_TIME | RD_ACCESS_TIME | (1 << 24)) // 0x010F1111
    # define FPGA_GPMC_CONFIG6        (WR_ACCESS_TIME | (3 << 16) | (1 << 31)) // 0x8F030000

    # define FPGA_GPMC_CONFIG_BASE        (GPMC_CONFIG_CS0 + (7 * GPMC_CONFIG_WIDTH))
    # define FPGA_BASE_ADD            0x38000000 /* CS7 */
    # define FPGA_MEM_SIZE            GPMC_SIZE_16M



#else

        // --------------------Eli.M 25/11/2008 ---------------------
        {
        //Configuring CS7 for FPGA
        #define        GPMC_CLK                150 //150MHZ
        #define     GPMC_CLK_PERIOD            (1000000/GPMC_CLK) // pico sec


        //CS = 50nsec 0-50ns    ----|__________|--------
        //RD cycle time = 55ns
        //WR cycle time = 55ns
        //OE = 40ns   5-45ns    -----|________|---------
        //WR = 40ns   5-45ns    -----|________|---------
        //RD acsess time = 45n
        //WR acsess time = 45n

        #define     RD_CYCLE_TIME_VAL       ((( 55/*ns*/ * 1000)/GPMC_CLK_PERIOD)             & 0x1F)
        #define     WR_CYCLE_TIME_VAL        ((( 55/*ns*/ * 1000)/GPMC_CLK_PERIOD)             & 0x1F)
        #define     CS_ONTIME_VAL            0
        #define     CS_RD_OFFTIME_VAL        ((CS_ONTIME_VAL + (50/*ns*/ * 1000)/GPMC_CLK_PERIOD) & 0x1F)
        #define     CS_WR_OFFTIME_VAL        CS_RD_OFFTIME_VAL
        #define     CS_OFFTIME_VAL          CS_RD_OFFTIME_VAL
        #define     OE_ONTIME_VAL            ((CS_ONTIME_VAL + (7/*ns*/ * 1000)/GPMC_CLK_PERIOD) & 0x0F)
        #define     OE_OFFTIME_VAL            ((CS_OFFTIME_VAL - (7/*ns*/ * 1000)/GPMC_CLK_PERIOD) & 0x1F)
        #define        WR_ONTIME_VAL            OE_ONTIME_VAL
        #define        WR_OFFTIME_VAL            OE_OFFTIME_VAL
        #define     RD_ACCESS_TIME_VAL        OE_OFFTIME_VAL
        #define     WR_ACCESS_TIME_VAL        RD_ACCESS_TIME_VAL
        #define        CYCLE2CYCLE_DELAY_EN    ((0X1)<<7)
        #define        CYCLE2CYCLE_DELAY_VAL    0XF            //    (((100/*NS*/ * 1000)/GPMC_CLK_PERIOD) & 0xF)

        #define     RD_CYCLE_TIME        (RD_CYCLE_TIME_VAL        << 0)
        #define     WR_CYCLE_TIME        (WR_CYCLE_TIME_VAL        << 8)
        #define     CS_ONTIME            (CS_ONTIME_VAL            << 0)
        #define     CS_RD_OFFTIME        (CS_RD_OFFTIME_VAL        << 8)
        #define     CS_WR_OFFTIME        (CS_WR_OFFTIME_VAL        << 16)
        #define     OE_ONTIME            (OE_ONTIME_VAL            << 0)
        #define     OE_OFFTIME            (OE_OFFTIME_VAL            << 8)
        #define        WR_ONTIME            (OE_ONTIME_VAL            << 16)
        #define        WR_OFFTIME            (OE_OFFTIME_VAL            << 24)
        #define     RD_ACCESS_TIME        (RD_ACCESS_TIME_VAL        << 16)
        #define     WR_ACCESS_TIME        (RD_ACCESS_TIME_VAL        << 24)
        #define     CYCLE2CYCLE_DELAY    (CYCLE2CYCLE_DELAY_VAL << 8)
        # define FPGA_GPMC_CONFIG1        0x01801000 // 0x00C01000
        # define FPGA_GPMC_CONFIG2        (CS_WR_OFFTIME | CS_RD_OFFTIME | CS_ONTIME)                  // 0x00101000
        # define FPGA_GPMC_CONFIG3        0x00020201
        # define FPGA_GPMC_CONFIG4        (OE_ONTIME | OE_OFFTIME | WR_ONTIME | WR_OFFTIME)            // 0x10031003
        # define FPGA_GPMC_CONFIG5        (RD_CYCLE_TIME | WR_CYCLE_TIME | RD_ACCESS_TIME | (1 << 24)) // 0x010F1111
        # define FPGA_GPMC_CONFIG6        (WR_ACCESS_TIME | CYCLE2CYCLE_DELAY_EN |CYCLE2CYCLE_DELAY | (3 << 16) | (1 << 31) ) // 0x8F030000
        # define FPGA_GPMC_CONFIG_BASE        (GPMC_CONFIG_CS0 + (7 * GPMC_CONFIG_WIDTH))
        # define FPGA_BASE_ADD            0x38000000 /* CS7 */
        # define FPGA_MEM_SIZE            GPMC_SIZE_16M



#endif

    static u32 gpmc_fpga[GPMC_MAX_REG] = {
        FPGA_GPMC_CONFIG1,
        FPGA_GPMC_CONFIG2,
        FPGA_GPMC_CONFIG3,
        FPGA_GPMC_CONFIG4,
        FPGA_GPMC_CONFIG5,
        FPGA_GPMC_CONFIG6, 0
    };

#if 0
    // ====== DEBUG !!!!!!!!!!!!!!
    for (i=0; i < GPMC_MAX_REG; i++)
        printf ("gpmc_fpga[%d] = 0x%.8X\n", i, gpmc_fpga[i]);
#endif

    gpmc_config = gpmc_fpga;
    gpmc_base   = FPGA_GPMC_CONFIG_BASE;
    base        = FPGA_BASE_ADD;
    size        = FPGA_MEM_SIZE;
    //Configure the GPMC CS7
    enable_gpmc_config(gpmc_config, gpmc_base, base, size);
#if 0
    //Read Test For CS testing
    while (1) { // for(testcounter=0;testcounter<1000;testcounter++){
        unsigned short testval;

        testval = (unsigned short)( __raw_readl(FPGA_BASE_ADD) & 0xFFFF);
        testval = (unsigned short)( __raw_readl(FPGA_BASE_ADD) & 0xFFFF);
        sdelay(300);
        __raw_writel(0x55, FPGA_BASE_ADD);
        __raw_writel(0xAA, FPGA_BASE_ADD);
        __raw_writel(r0x33, FPGA_BASE_ADD);
        sdelay(1000);
    }//for
#endif
    }

}

0 Vijay over 16 years ago in reply to Vijay

Intellectual 680 points

Hi Brandon,

Some more information:

Below are the register settings...

OMAP3EVM # md 0x6e0001b0
6e0001b0: 01801000 00070700 00020201 06010601 ................
6e0001c0: 01060808 86030f80 00000f78 ffffffff ........x.......

We would like to know why the read and write sequence are not with the same time setting as we wish too.

0 BrandonAzbell over 16 years ago in reply to Vijay

TI__Guru 64540 points

Thank you for the printout of the register settings. So far, I haven't determined where the source of the issue is. From how I interpret your data, the nCS high period is getting extended by 2X between successive accesses, correct?

One thing that I would suggest changing is the GPMC_CONFIG1_7[24:23] from 0x3 to 0x1. The value of 0x3 is reserved. This is the ATTACHEDDEVICEPAGELENGTH field and the default is 0x0 which indicates 4 words. I realize you may not be trying to perform page accesses, which should be controlled by the READMULTIPLE and WRITEMULTIPLE fields both set to 0x0, or single access.

0 Eli Makdasi over 16 years ago in reply to BrandonAzbell

Prodigy 10 points

Hi,

I have configured the GPMC registers according your recomendation but i still get doubled read time comparing to write cycle.

The attache file is our u-boot which configure the GPMC registers.

if you have more ideas what can cause that you welcome.

Eli

0 santosh vastrad over 13 years ago in reply to Eli Makdasi

Expert 2060 points

hi vijay:

I am also doing same thing, that is connecting nand to GPMC_CS7. I need your u-boot modification to access nand,

I tried by changing u-boot still unable to get device id and manufacture id of the nand flash device.

16Gbit nand flash (2GB Hynix) (AM3703 processor).

expecting reply?

Thanks

santosh vastrad

0 hrishikesh choudhary over 13 years ago in reply to santosh vastrad

Expert 1390 points

Hi Vijay !!!

Can you let me know...what you are doing in the enable_gpmc_config(gpmc_config, gpmc_base, base, size); function.

In which register you are Updating this value.

I have stucked with the same problem... we have interfaced an External NAND of 32Gb through an FPGA. the Processor sends the control signal and Data signal to the FPGA and from there it is Routed to NAND.

This are My configurations :

OUT_REGL(GPMC_CONFIG, 0x00000002);

   OUT_REGL(GPMC_CONFIG1_1, 0x00010813);
   OUT_REGL(GPMC_CONFIG2_1, 0x001F1F00);
   OUT_REGL(GPMC_CONFIG3_1, 0x00030383);
   OUT_REGL(GPMC_CONFIG4_1, 0x1A001A00);
   OUT_REGL(GPMC_CONFIG5_1, 0x001D1F1F);
   OUT_REGL(GPMC_CONFIG6_1, 0x1D000505);
   OUT_REGL(GPMC_CONFIG7_1, 0x00000C5f);

...Can you let me what you are doing in the function enable_gpmc_config.

thanks and regard's

Hrishikesh.

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Configuring CS7 of the OMAP