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EMIFB Memory Error Interrupt

Takahiro Ogo
Genius 5940 points

Hi
I have a quetion about EMIFB(SDRAM) Interrupt in C6747/L137.

As DSP interrupt Map, C6747 can recieve "EMIFB Memory Error Interrupt"(EMIFB_INT: Event 60).
Please tel me how this interrupt occur.

For example, If  unexpected data is read from SDRAM to generate any glitch in SDRAM Clock line, this EMIFB_INT occurred ?

Best Regards.

  • 0
    TI__Mastermind 35645 points

    Hi Takao,

    Thanks for your post.

    Usually, there are protection checks implemented in the MPU unit on the device which takes care of address violation or protection violation, if any, during a memory access and throws an address error interrupt (MPU_ADDR_ERR_INT) and a protection interrupt (MPU_PROT_ERR_INT) if any violation happens due to an access in the MPU register space. Likewise, EMIFB_INT: Event 60 interrupt also occurs in this type of usecase

    The device supports two memory protection units and to be specific, MPU2 supports the EMIFB. Please refer Section 6.3, Table 6-7. MPU2 Registers in the OMAPL137 TRM as mentioned below, in which, kindly check IENSTAT & IENSET register details to set and check the status of memory error interrupts as below:

    http://www.ti.com/lit/ug/spruh92b/spruh92b.pdf

    Please also refer Section 5.13 for more understanding on MPU in the OMAPL137 datasheet as below:

    http://www.ti.com/lit/ds/symlink/omap-l137.pdf

    Thanks & regards,

    Sivaraj K

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  • 0 in reply to Sivaraj Kuppuraj
    Genius 5940 points

    Hi Sivaraj

    Thank you for your reply.

    I understood this interrupt by your favor.  

     (This interrupt doesn't seem to be my purpose.....)

     

    Thanks & regards,

    -Takao