DM6437 CLKOUT0 Jitter Specification

Daisuke,

We do not have any jitter spec for this clock output. Clockout timing is based on meeting setup and hold relative to data. CLK jitter is taken into account for the spec timings. We don't have a separate spec for clock output jitter and this is not something we characterize and specify at a device level.

 Looking at the PLL specs , the clockout jitter should be around +/-2.5% of the clock period . This number/data is ONLY to give a customer an idea of what to expect, and it should not be interpreted as a guarantee or a spec'd value

It should also be understood, that factors outside the chip/device, like noise on the IO etc, can also impact jitter and there is no control on that from the device side.

Tom