RE: C6670 SRIO Connection Problem

Please confirm which device are you looking at.  You say you are not able to get port_ok in loopback?  Please provide detail on what you are trying to do.  Port_ok is the most basic step and usually involves something physical in nature.  I've never seen an issue with establishing port_ok in loopback.  See:

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/255031.aspx

Regards,

Travis

Hi Travis,

I was trying with c6670 evm but later it was interchanged with TI C6614 evm by my colleague who told  that everything is similar just run your code.

then Iater i found that SRIO clk is 312.5Mhz in C6614 evm case instead of 250Mhz. so my pll setting changed to 0x241 MPY=8 instead of 0x251 ,MPY=250Mhz.

So after this I'm getting port ok at DSP end and also port is getting initialized at FPGA side.

BUt now I dont know actually how to go about in a simple transfer between dsp and fpga ??

Altera has provided a sample code for c6488 but not sure how will i modify the loopbackDioIsr.c which is my base for keystone devices.

Please provide a early reply .....

Thanks

Glad you figured out the refclk issue.  The TCI parts are not supported on the e2e forums, only with local FAE support.

Yes the C64x examples will be quite different from the Keystone examples.  Hopefully you have downloaded the MCSDK and you are referring to the example at:

C:\ti\pdk_C6670_1_1_2_6\packages\ti\drv\srio\example\SRIOLoopbackDioIsr

If so, there is a very small change to take it out of loopback and do chip-to-chip.  Please see:

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/170264/752157.aspx#752157

The very first post explains it.

Regards,

Travis

Thanks  Travis,

I have already changed from loopback  to CSL_SRIO_SetNormalMode for all ports 0 to 3 ,

actually my fpga has one port working at 1x,

  i get port initialized at fpga side  also port ok for one port at dsp side. all other 3 ports fail,

is it fine to initialize 4 ports and use 1port @ 1x ,  at dsp end?

My concerns ...

But  anything extra to be done to do a simple tranaction through this port.

I dont know exactly how to modify loopbackDioIsr.c code ..

My understanding od code

from main()==>

 srio device initilaizatiuon ===> in device_srio_loopback.c code changes made to get port ok  for one port after that i made to skip other ports ...

then goes to a task "dioExampleTask"

from there goes to dioSocketsWithISR ---I think this is the one i need to chnge for a  simple srio tranaction through 1 port..  is it??

there some interrupt routing is done ...i didn't understand that..====>

buffer initialization then===>

then i changed  bindInfo.dio.idSize =0===>//my fpga is 8 bit dev id ...  is this correct??

then i changed to.dio.rapidIOLSB= fpga memory address also  to.dio.dstID = fpga device id ...is it correct?

then socket is sent Srio_sockSend_DIO===> what does it means

then it closes socket then prints failed at end

ISR didn't happen within set time - 100000 cycles. Example failed !!!
Error: Loopback DIO ISR example for Write operation failed

Am I going in right direction in dsp side or i should focus something else ....

Please help in this regard....

Thanks

Thanks Travis,

I have already changed from loopback to CSL_SRIO_SetNormalMode for all ports 0 to 3 ,

actually my fpga has one port working at 1x, i get port initialized at fpga side also port ok for one port at dsp side. all other 3 ports fail,

is it fine to initialize 4 ports and use 1port @ 1x , at dsp end?

My concerns ... But anything extra to be done to do a simple tranaction through this port.

I dont know exactly how to modify loopbackDioIsr.c code ..

My understanding of code

from main()==> srio device initilaizatiuon ===> in device_srio_loopback.c code changes made to get port ok for one port after that i made to skip other ports ...

then goes to a task "dioExampleTask"

from there goes to dioSocketsWithISR ---I think this is the one i need to change for a simple srio tranaction through 1 port.. is it??

there some interrupt routing is done ...i didn't understand that..=

===> buffer initialization

then===> then i changed bindInfo.dio.idSize =0===>//my fpga is 8 bit dev id ... is this correct??

then i changed to.dio.rapidIOLSB= fpga memory address also to.dio.dstID = fpga device id ...is it correct?

then socket is sent Srio_sockSend_DIO===> what does it means

then it closes socket then prints failed at end

ISR didn't happen within set time - 100000 cycles. Example failed !!! Error: Loopback DIO ISR example for Write operation failed

Am I going in right direction in dsp side or i should focus something else ....

Please help in this regard....

Thanks

Hi Travis ,

Thanks for your time ...

We had a issue with device ID at fpga side , now that it is solved  fpga supports 16 bit ID .

and i'm able to complete the full write and read commands where i commented out verify section(since that will never match).

but

 to.dio.rapidIOMSB    = 0x0;
            to.dio.rapidIOLSB    = onchip_addr;// fpga address ??

how to check data is written since nwrite is completed successfully.

if i change device id

to.dio.dstID         ==other than fpga rio id then nwrite doesn't complete successfully

if the id is correctly set then write happens successfully.

Debug(Core 0): DIO Socket (0) Send for iteration 0
Debug(Core 0): ISR Count: 1
Debug(Core 0): DIO Socket (1) Send for iteration 0
Debug(Core 0): ISR Count: 2
Debug(Core 0): DIO Socket (2) Send for iteration 0
Debug(Core 0): ISR Count: 3
Debug(Core 0): DIO Socket (0) Send for iteration 1
Debug(Core 0): ISR Count: 4
Debug(Core 0): DIO Socket (1) Send for iteration 1
Debug(Core 0): ISR Count: 5
Debug(Core 0): DIO Socket (2) Send for iteration 1
Debug(Core 0): ISR Count: 6
Debug(Core 0): DIO Socket (0) Send for iteration 2
Debug(Core 0): ISR Count: 7
Debug(Core 0): DIO Socket (1) Send for iteration 2
Debug(Core 0): ISR Count: 8
Debug(Core 0): DIO Socket (2) Send for iteration 2
Debug(Core 0): ISR Count: 9
Debug(Core 0): Transfer Completion without Errors - 9
Debug(Core 0): Transfer Completion with Errors    - 0
Debug(Core 0): DIO Transfer Data Validated for all iterations
Debug(Core 0): DIO Data Transfer (WRITE) with Interrupts Example Passed

is that mean srio packets reaches fpga and dsp gets an ack for that??

please clarify..

Thanks

NWRITE doesn't have a logical layer response packet.  The CC in the LSU will say good completion, as soon as the packet is moved from the logical layer to the physical layer for transmit inside the SRIO peripheral.  The packet doesn't actually have to be sent at all, it could still be inside the physical layer buffers.  NWRITE_R does have a response packet associated with it.  So, if the CC in the LSU says good completion for an NWRITE_R, then you know the packet has been transmitted and the destination device has received it and sent a response packet back to the DSP acknowledging that it was written to memory. 

What I talked about above were logical layer responses.  In the physical layer, all packets are acknowledged with control symbols, either a packet accepted or packet not accepted control symbol.  These are really used for hardware purposes for guaranteed delivery, they are not really accessible via SW.

Hope that helps,

Travis

Thanks Travis ,

Actually I checked  SPn_ACKID_STAT its updating after each ISR count  and at fpga side also i get same ackID(through register check)

Does that confirm fpga side is receiving packets??

But one thing the address that  i mentioned below is local address of memory in fpga ??? or any translation needed??

since fpga side have avalon memory address scheme and is it the same ??

 to.dio.rapidIOMSB    = 0x0;
            to.dio.rapidIOLSB    = onchip_addr;// fpga address or any translated address??

Please help.

Thanks.

Hi travis,

we are using your keystone device but not much help is given .....please help us to upgrade our old 64xx to c66xx

please leave all topics ...i somehow made to sent the packets....

please tell me when we do a DIO socket send  at receiving point(fpga) whether the buffer values are presented

in order or in different order..

if yes how to control that??

please help...

urgent..

HI travis,

Finally we are able to send and receive packets from dsp to fpga ...

Also I found out that rio core is big endian, it is mentioned in sprugw1b 2-57, thats why it reverses.

same thing happened from fpga to dsp.

Thanks for all your support

we really appreciate your responses, time and patience in understanding our queries.

Nitin

Glad you were successful on the DSP to FPGA communication.  I don't have a lot of exposure to FPGA SRIO solutions.  All SRIO transactions are sent using BE packet format as dictated by the RapidIO standard.  If the DSP is in LE, the swapping boundaries are defined by PER_SET_CNTL 31:28.  Most leave it in 1B swap boundaries, which has the effect of same byte address on both the BE and LE devices.

Regards,

Travis

Hi Travis ,

Sorry for interrupting you again..

Now I'm trying srio on custom board  with c6670 ....(it is similar to 6614)

which uses ref srio clk =250MHz ,

so pll setting is 0x251 ...

i get port initialized at fpga side  after

/* Configuration has been completed. */
    CSL_SRIO_SetBootComplete(hSrio, 1);

but it is stuck at port ok===> i'm not getting port ok....

please help....

Hi travis,

I'm not able to open the srio registers and see error status...

whenever i open i get following errors

C66xx_0: Trouble Reading Memory Block at 0x2900000 on Page 0 of Length 0x4: Error 0x00000002/-1194 Error during: Memory,  The memory ID is not supported by the hardware.  

Please provide more details, what is the desired data rate?  How are you programming the CFGRX/TX registers, with RATESCALE?  Have you looked at the vrange setting?  http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/255031.aspx

Table 3-7 has the PLL settings that are supported for various refclk.

How are you trying to access the error status registers, via CCS?

Hi,

Now it started working after giving a reset to link partner(fpga)

but not able to access the error status registers through ccs register tab...

that i used to access when connected to evm.

Hi,

I'm trying to get a better understanding of your system configuration. How are you physically connecting your custom board to your host machine running CCS? How is your custom board initialized? What is performed in that initialization sequence?

Thanks,

Clinton

To add to Clinton's questions, can you access other device registers on your custom board?  Can you access other SRIO peripheral registers, just not the error status registers?  There is nothing special about these registers, so if you can access any registers, these should be accessible too.

Regards,

Travis