Okay, my problem seems to have a lengthy description, so I apologize:
I am using:
CCS 5.4.0
Bios 6.35.3
XDC 3.25.2
A custom 28335 based mainly on an EZDSP board
I recently converted a project from DSP/BIOS and have the program executing correctly (I think) except for the ADC and PWM calculations.
The hardware is basically a DC/DC converter with the PWMs controlling IGBTs.
The ADC is initialized like so:
In the program a HWI is triggered via the PIE 1.6 ADCINT, which posts a SWI depending on if a SEQ1 or SEQ2 conversion took place. In the SEQ1 ISR the first thing done is set a flag for which PWM triggered the conversion, like so:
if (EPwm1Regs.ETFLG.bit.SOCA == 1) // conversion triggered by PWM phase A
{
EPwm1Regs.ETCLR.bit.SOCA = 1; // clear the flag denoting SOC started by phase A
PWMState = STATE_EOC_PHASE_A; // Denote that the PWM module state is such that phase A conversion just completed
phaseA = phaseA+1;
}
Then, it checks whether the ADC conversion took the measurement corresponding to the PWM trigger.
if (AdcRegs.ADCASEQSR.bit.SEQ1_STATE == STATE_EOC_PHASE_A && PWMState == STATE_EOC_PHASE_A) // Measurements corresponding to phase A just completed
{
WrnFlags.Wrn0.bit.L0_ADCPHS = 0; // Clear Warning flag, since the ADC and PWM phases match
From there it pulls the measurement from the shadow register, scales it, and stores it. Then it looks to be sure it’s not in an overvoltage condition, then see’s if it happened fast enough to go into the current loop via another SWI.
if ( (DSP_State != S_INIT) && (EQep1Regs.QFLG.bit.INT != 1) && (EPwm1Regs.TBCTR > pwmfullduty/2)) // If more than 1/4 PWM period has passed since SOC was initiated
{
SetFault(); // Set DSP to fault state
ErrFlags.Err1.bit.L6_ADCSLOW = 1; // Set flag indicating ADC conversion process too slow.
}
-When I execute this in DSP/BIOS, with a cpuFreq of 150MHz, and a PWM frequency of 4kHz, it has very even numbers for debugging counters I put in each of the Phase A, Phase B, and Phase C measurement loops (even though Phase C is not being used, it is still in there because of the hardware).
-When nothing is changed in the setup or configuration code, except for the conversion to SYS/BIOS, the measurement loop counts are all over the place, usually excluding phase B.
This seems to be some kind of synchronization problem, but I can’t figure out why. The PLLs lock, and everything else seems to be operating as expected.
There is one difference, however. Due to size constraints, I am no longer able to run the .econst section out of RAM, and have kept it in flash. Other than that, everything else about the code is identical.
Here are the map files for DSP/BIOS
And SYS/BIOS
