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pandaboard ES 4460 external GPMC clock line trouble

Edward Bockhoefer
Prodigy 120 points

Other Parts Discussed in Thread: OMAP3530

Greetings,

I will be connecting the external GPMC interface of an OMAP4460 to communicate with internal memory in a Xilinx FPGA. We've already done this successfully with an OMAP3530 design. I was wondering if it was possible as a test to configure the OMAP4 GPMC controller to see the GPMC_CLK pin oscillate on the Panda ES board Jumper J6 breakout on pin 23 (gpmc_clk) without anything connected to the board breakout? I know the GPMC_FCLK is not free running. So I wrote a while true loop in a Linux script to continuously read the base memory address on chip select 0 hoping to trigger and capture the clock line on an oscilloscope through PIO mode at the command line . No DMA setup. Just using the devmem2 program to remap a physical to virtual address at the CS0 base and read. But I see nothing on the scope for the clk line.

I have the GPMC_CLK line set up in the u-boot MUX to be feed back as an input. Feed back was needed in omap35xx to sync clock line.

    {GPMC_CLK, (IEN | PTD | DIS | M3)},            /* gpio_55 */

I have followed the TRM guidelines for the GPMC NOR set-up in sync mod.

15.4.5 GPMC Basic Programming Model
15.4.5.3 GPMC Configuration in NOR Mode
 

We use an internal program we wrote here to simplify the reading of omap registers. My GPMC configuration is listed below in the output:

# ./omap4regs -u gpmc:cs0
GPMC Chip Select: 0 Information
GPMC_CONFIG1_0: 0x79001200
        Sync. wrapping burst supported? No
        Read Access type    : Multiple
        Read type           : Sync
        Write Access type   : Multiple
        Write type          : Sync
        Output Act. time    : 0
        Page length         : 16 words
        Wait pin monitored for read?    No
        Wait pin monitored for write?   No
        WAITMONITORINGTIME  : 0
        Wait input pin      : WAIT0
        Device Size         : 16-bit
        Device Type         : NOR Flash
        Multiplexed A&D dev : Yes
        TIMEPARAGRANULARITY : 0
        GPMCFCLKDIVIDER     : GPMC_FCLK
GPMC_CONFIG2_0: 0x000E0E00
        CSWROFFTIME         : 14 GPMC_FCLK cycle(s)
        CSRDOFFTIME         : 14 GPMC_FCLK cycle(s)
        CSEXTRADELAY        : 0
        CSONTIME            : 00 GPMC_FCLK cycle(s)
GPMC_CONFIG3_0: 0x00020200
        ADVWROFFTIME        : 02 GPMC_FCLK cycle(s)
        ADVRDOFFTIME        : 02 GPMC_FCLK cycle(s)
        ADVEXTRADELAY       : 0
        ADVONTIME           : 00 GPMC_FCLK cycle(s)
GPMC_CONFIG4_0: 0x0B040B04
        WEOFFTIME           : 11 GPMC_FCLK cycle(s)
        WEEXTRADELAY        : 0
        WEONTIME            : 04 GPMC_FCLK cycle(s)
        OEOFFTIME           : 11 GPMC_FCLK cycle(s)
        OEEXTRADELAY        : 0
        OEONTIME            : 04 GPMC_FCLK cycle(s)
GPMC_CONFIG5_0: 0x02080E0E
        PAGEBURSTACCESSTIME : 02 GPMC_FCLK cycle(s)
        RDACCESSTIME        : 08 GPMC_FCLK cycle(s)
        WRCYCLETIME         : 14 GPMC_FCLK cycle(s)
        RDCYCLETIME         : 14 GPMC_FCLK cycle(s)
GPMC_CONFIG6_0: 0x88030000
        WRACCESSTIME        : 08 GPMC_FCLK cycle(s)
        WRDATAONADMUXBUS    : 03 GPMC_FCLK ^edge(s)
        CYCLE2CYCLEDELAY    : 00 GPMC_FCLK cycle(s)
        CYCLE2CYCLESAMECSEN : 0
        CYCLE2CYCLEDIFFCSEN : 0
        BUSTURNAROUND       : 00 GPMC_FCLK cycle(s)
GPMC_CONFIG7_0: 0x00000868
        MASKADDRESS         : 128 MBytes
        CS Enabled?         : Yes
        BASEADDRESS         : 0x28000000

I then contentiously read address 0x28000000 with devmem2 and CLK line does not trigger scope. Any ideas?

Regards,

Ed

  • 0
    TI__Genius 10965 points

    Hi Edward,

    Did you set all PRCM registers. 

    Look at especially the following sub-chapter :

    "GPMC Clocks Frequency Scaling Constraints"

    and CM_SHADOW_FREQ_CONFIG1 register

    Please check status of CM_L3_2_GPMC_CLKCTRL[] register. We have to check if it is in idle mode.

    Regards,

    Boyko

  • 0 in reply to Boyko Kazakov
    Prodigy 120 points

    Hi Boyko,

    I'll need to verify the PRCM registers tomorrow. I got pulled off this project to put out a different fire today. I noticed that PRCM registers seem to be completely different on this OMAP4 Cortex-A9 than they were on the Cortex A8 of the OMAP3530. Not just a simple GPMC base address change with the same register offsets between two processors.

    Are there any PRCM registers I should be looking at specifically?

    I was able to verify that PLL is in lock mode and not in idle from what I understand of the TRM.

    -------------------------------------------------------

    CM_SHADOW_FREQ_CONFIG1 register.
    DLL is reset automatically during the frequency change hardware sequence, Enables the DPLL in lock mode.
    # ./devmem2 0x4A004260     
    /dev/mem opened.
    Memory mapped at address 0xb6f63000.
    Value at address 0x4A004260 (0xb6f63260): 0xF08

    --------------------------------------------------------

    CM_L3_2_GPMC_CLKCTRL register.
    Address 0x4A008828 reads a value of 0x01. Module is fully functional, including INTRCONN. That is not in idle and module is not performing transition: wakeup, or sleep, or sleep abortion.
    # ./devmem2 0x4A008828
    /dev/mem opened.
    Memory mapped at address 0xb6fd9000.
    Value at address 0x4A008828 (0xb6fd9828): 0x1

    Take care,

    Ed

  • 0 in reply to Edward Bockhoefer
    TI__Genius 10965 points

    Hi Edward,

    Do You have any progress on this case? Can you also check

    CM_SHADOW_FREQ_CONFIG2[]

    Regards, 

    Boyko

  • 0 in reply to Boyko Kazakov
    Prodigy 120 points

    Hi Boyko,

    Sorry for the late response. I got it!

    I had the GPMC_CLK_MUXMODE and GPMC_CLK_INPUTENABLE
    fields in the CONTROL_CORE_PAD0_GPMC_NWP_PAD1_GPMC_CLK register configured incorrectly. I thought I had the gpmc_clk line set as an input correctly in u-boot but I was wrong. I corrected it and now see 200Mhz burst reads on the gpmc_clk line with an o-scope.

    Do you know how fast I can bust the gpmc_clk line on the omap4? I think the TRM stated I could drive the gpmc clk line up to 400Mhz as long as anything else connected on the internal GPMC bus could run at 400Mhz. That is my Micron PoP RAM is 2.5ns (400Mhz). Maybe I'm dividing it down by 2 in one of the configuration registers. I see in GPMC_CONFIG1_0 that GPMCFCLKDIVIDER field is set to run at GPMC_FCLK (not divided down).

    Thank you for the help!

    Ed