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Camera ISP IN OMAP 3530

In Camera ISP the following signals can be configured as either output(internally generated) or input(externally generated).

cam_hs, cam_vs, cam_fld,cam_global_reset

I am not clear about the Signals and its configuration.Can any one explain about the signals?

Is there any advantage for internally generated one?

Can any one explain the purpose of internally generated one?

Thanks and Regards,

Kathir

  • When connecting two video parts together, you must make sure they are both talking the same language, particularly when it comes to knowing where a frame begins and ends (done w/ use of hsync, vsync, and field id).  This is normally done one of two ways 

       1) by choosing a standard such as BT.656 that dictate the video timing protocol (HSYNC, VSYNC, Field ID); in such case video timing is embeded in data stream (no hsync, vsync, fld pins necessary)

       2)  by configuring one part as a master and the other as a slave (for the purpose of video timing)

    Our OMAP part can be configured as both a master (internal generated signals) or a slave (externally generated) for maximum flexibility and compatibility.

  • To elaborate on what Juan is saying:

    keshan said:
    Can any one explain about the signals?

    cam_hs is the horizontal sync, that is, it is a signal in the form of a wire that pulses with each new line of video, allowing whichever device is the slave to know when to expect or to provide the next line.

    cam_vs is the vertical sync, that is, it is a signal very similar to the horizontal sync only in the vertical direction, it pulses for each new frame so that the slave device knows when to expect or to provide the next frame.

    cam_fld is the field identification signal, this signal only really applies to interlaced content, as it signifies which field (odd/even) is currently being transmitted.

    cam_global_reset appears to deal with still camera operations, and in particular is the global release shutter signal (I am not as familiar with this one as I mostly just deal with video signals).

    keshan said:
    Is there any advantage for internally generated one?

    Not necessarily, it does not really matter whom generates the timing signals, as long as both master and slave agree upon them. I suppose the advantage of internally generated signals would be that you configure them within the device itself as opposed to writing to registers in an external video device, but again this is really fairly arbitrary.

    keshan said:
    Can any one explain the purpose of internally generated one?

    The internally generated signals exist such that you could communicate with a device that is unable to generate its own timing and synchronization signals.