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BANKALLOCATION Parameter

sureshkumar8095
Intellectual 510 points

Hi all

  Regarding memory optimization i am refering SPRUF98B omap 3530 trm. In page no 1322 and 1333 given that bank allocation parameters and latencies.

I wanted to make use of  bank allocation paramer and 4 banks ,i wrote a simple program and executed in single bank and 4 bank architecture by confiuring the reg

SDRC_MCFG_0 | =((0x010<<8)|(0x1<<6)|(0x1<<0)); But i didnt get any performence,please try to sort out this problem..

My assumption is Keeping the data in different banks reduces the opening and closing time . By this feature we can make make perticular region as cache..

thanks and regards

sureshkumar 

  • TI__Mastermind 41665 points

    Adjusting the BANKALLOCATION value can adjust latencies in memory accesses, but having the cache in place can frusterate measuring the differences in performance, which is possibly why you are seeing little difference.

    sureshkumar said:
    By this feature we can make make perticular region as cache..

    I am not sure what you mean by this, the cacheability of a region of memory is controlled elsewhere.

  • Intellectual 510 points

    Hi all,

        I have divided total SDRAM (DDR)of 128MB to 4, 32MB blocks(DDR2,DDR3,DDR4,DDR5). It is working fine in simulator and when i work with the same memory banks in emulator it is working fine in DEBUG mode but in not working in RELEASE mode. I cant say a particular error happening it some times stops in the middle, sometimes gives some memory mapping errors. but it is working fine in debug mode. Can i get a sollution so that the issue can be resolved.

    another thing i want to ask is whether dividing the external memory into banks gives any optimization or not? 

    can you say  any other memory optimization techniques to work with?

    Thanks in advance,

    With regards,

    Suresh.

     

  • in reply to sureshkumar8095
    TI__Guru 64470 points

    It seems there may be some confusion as to what is really being meant by the use of the BANKALLOCATION setting and how it relates to the physical architecture of the DRAM device.

    Generally, many of the DRAM devices out there are in fact implemented with 4 physical memory banks.  How you address these, access them, activate a row, etc. is dependent on the concatenation of the BANK-ROW-COLUMN addressing scheme.  This addressing scheme is configured by the BANKALLOCATION bits.
    Page 1323 describes the benefits of modifying the addressing scheme from the traditional BANK-ROW-COLUMN to something else.  Essentially, you are trying to reduce the amount of overhead spent on deactivating and reactivating rows in the DRAM.