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OMAP3530 BIOS related

sureshkumar8095
Intellectual 510 points
Other Parts Discussed in Thread: OMAP3530

Hi all

I am having following doubts  regarding omap3530

1 When i select omap3530evm in dsp/bios platform it is showing DSP speed is 330MHz but c64x+ runs at 430MHz is it?

2 what should i select in GEM True completion Bit section in global settings in 64plus what it mean?

3 I am planning Divide the external memory (CE0)4 banks is it really worth? it is given inTRM ,but i execute the sample program in hardware i dint find any improvement. in cycles?   what is the procedure for the above issue.

Thanks and regards

sureshkumar

  • 0
    TI__Mastermind 41665 points

    sureshkumar said:
    1 When i select omap3530evm in dsp/bios platform it is showing DSP speed is 330MHz but c64x+ runs at 430MHz is it?

    The speed the C64x+ is running at will depend on your GEL file if you are working with CCS, or by how the cpufreq driver in Linux configures it if you are stand alone. The BIOS setting is something you have to enter, it is not something that BIOS is reading from the device. The BIOS configuration file uses the speed value you provide it to configure the timers so that your BIOS instance operates at the desired speed, for example such that PRD functions happen at the correct rate.

    sureshkumar said:
    2 what should i select in GEM True completion Bit section in global settings in 64plus what it mean?

    This setting is described on page 169 of SPRU403, this value looks to deal with how the BCACHE API will wait for a writeback to complete. Unfortunately I am not that familiar with what this means outside of the document, it looks like it is trying to work around some issue with verifying writeback completion, I may have to look into this one further.

    sureshkumar said:
    3 I am planning Divide the external memory (CE0)4 banks is it really worth? it is given inTRM ,but i execute the sample program in hardware i dint find any improvement. in cycles?   what is the procedure for the above issue.

    Could you point out what you are referencing in the TRM? The DDR can have 4 banks though I am not sure exactly how this applies to your optimization. See http://community.ti.com/forums/t/2978.aspx