Issue with Micron- MT42L256M32D2LK-18WTA - LPDDR2 on OMAP4470

MihirShah

We have an OMAP4470 with Micron- MT42L256M32D2LK-18WTA - LPDDR2.

The system is booting and interfaces are functional. The new things we observed is high heating of LPDDR2 as well as HDMI Output display blinking where these are more overlays.

We used the same hardware with Elpida LPDDR2 and the same release works perfectly fine. It seems Panda and OMAP4470 releases are tunned for Elpida LPDDR2 timings.

We are using kernel 3.4 blow is the details of kernel if needed

git clone git://git.omapzoom.org/kernel/omap.git kernel/android-3.4
cd kernel/android-3.4
git checkout e9515a74fe28cf097adf37875acc03476cb4770a

INFO:

/*
* SDRAM memory data
*/
struct ddr_device_info lpddr2_elpida_4G_S4_x2_info = {
.type = DDR_TYPE_LPDDR2_S4,
.density = DDR_DENSITY_8Gb,
.io_width = DDR_IO_WIDTH_32,
.cs1_used = true,
.cal_resistors_per_cs = false,
.manufacturer = "Elpida"
};

Timings:

struct lpddr2_timings lpddr2_elpida_4G_S4_timings[] = {
/* Speed bin 1066(533 MHz) */
[0] = {
.max_freq = 533333333,
.min_freq = 10000000,
.tRPab = 21000,
.tRCD = 18000,
.tWR = 15000,
.tRAS_min = 42000,
.tRRD = 10000,
.tWTR = 7500,
.tXP = 7500,
.tRTP = 7500,
.tCKESR = 15000,
.tDQSCK_max = 5500,
.tFAW = 50000,
.tZQCS = 90000,
.tZQCL = 360000,
.tZQinit = 1000000,
.tRAS_max_ns = 70000,
.tRTW = 7500,
.tAONPD = 1000,
.tDQSCK_max_derated = 5620,
},
}

Kindly suggest us what is wrong here to release the issues....

--Mihir

over 11 years ago

0 Yordan Kovachev over 11 years ago

TI__Guru**** 161600 points

Hello,

The above timings seem to be correct.

But there are additional EMIF settings in the board file in arch/arm/mach-omap2/ . Which board file are you using for your board?

For example the board file for Pandaboard (board-omap4panda.c) has the following settings:

#if defined(CONFIG_TI_EMIF) || defined(CONFIG_TI_EMIF_MODULE)
    omap_emif_set_device_details(1, &lpddr2_elpida_2G_S4_x2_info,
            lpddr2_elpida_2G_S4_timings,
            ARRAY_SIZE(lpddr2_elpida_2G_S4_timings),
            &lpddr2_elpida_S4_min_tck, NULL);
    omap_emif_set_device_details(2, &lpddr2_elpida_2G_S4_x2_info,
            lpddr2_elpida_2G_S4_timings,
            ARRAY_SIZE(lpddr2_elpida_2G_S4_timings),
            &lpddr2_elpida_S4_min_tck, NULL);
#endif

But you use 4G_S4 lpddr structure from the common-board-devices.c file.

Could you try modifying your board file like (board-44xx-tablet.c):

#if defined(CONFIG_TI_EMIF) || defined(CONFIG_TI_EMIF_MODULE)
    if (cpu_is_omap447x()) {
        omap_emif_set_device_details(1, &lpddr2_elpida_4G_S4_info,
                lpddr2_elpida_4G_S4_timings,
                ARRAY_SIZE(lpddr2_elpida_4G_S4_timings),
                &lpddr2_elpida_S4_min_tck, &custom_configs);
        omap_emif_set_device_details(2, &lpddr2_elpida_4G_S4_info,
                lpddr2_elpida_4G_S4_timings,
                ARRAY_SIZE(lpddr2_elpida_4G_S4_timings),
                &lpddr2_elpida_S4_min_tck, &custom_configs);
    } else {
        omap_emif_set_device_details(1, &lpddr2_elpida_2G_S4_x2_info,
                lpddr2_elpida_2G_S4_timings,
                ARRAY_SIZE(lpddr2_elpida_2G_S4_timings),
                &lpddr2_elpida_S4_min_tck, &custom_configs);
        omap_emif_set_device_details(2, &lpddr2_elpida_2G_S4_x2_info,
                lpddr2_elpida_2G_S4_timings,
                ARRAY_SIZE(lpddr2_elpida_2G_S4_timings),
                &lpddr2_elpida_S4_min_tck, &custom_configs);
    }

Best Regards,

Yordan

0 MihirShah over 11 years ago in reply to Yordan Kovachev

Prodigy 240 points

Thanks Yordan for the reply,

We are using this configuration in board-omap4panda.c

#if defined(CONFIG_TI_EMIF) || defined(CONFIG_TI_EMIF_MODULE)
    omap_emif_set_device_details(1, &lpddr2_elpida_4G_S4_info,
  lpddr2_elpida_4G_S4_timings,
            ARRAY_SIZE(lpddr2_elpida_4G_S4_timings),
            &lpddr2_elpida_S4_min_tck, NULL);
    omap_emif_set_device_details(2, &lpddr2_elpida_4G_S4_info,
  lpddr2_elpida_4G_S4_timings,
            ARRAY_SIZE(lpddr2_elpida_4G_S4_timings),
            &lpddr2_elpida_S4_min_tck, NULL);
#endif

And we had tried with this configuration also

#if defined(CONFIG_TI_EMIF) || defined(CONFIG_TI_EMIF_MODULE)
    omap_emif_set_device_details(1, &lpddr2_elpida_4G_S4_x2_info,
  lpddr2_elpida_4G_S4_timings,
            ARRAY_SIZE(lpddr2_elpida_4G_S4_timings),
            &lpddr2_elpida_S4_min_tck, NULL);
    omap_emif_set_device_details(2, &lpddr2_elpida_4G_S4_x2_info,
  lpddr2_elpida_4G_S4_timings,
            ARRAY_SIZE(lpddr2_elpida_4G_S4_timings),
            &lpddr2_elpida_S4_min_tck, NULL);
#endif

Even though for both timings the behavior is same the display will be blinking. with this error log when ever it blinks

omapdss DISPC error: FIFO UNDERFLOW on gfx, disabling the overlay

omapdss DISPC error: mgr or device is NULL

We are using android 4AJ.2.5 release, This release works fine with Elpida memory on our board.

On same hardware with Micron memory, with same kernel and changes of timings also we see the blinking behavior and ram heating issues.

If the timings are correct what may be the issue?

Regards,

Mihir

0 Yordan Kovachev over 11 years ago in reply to MihirShah

TI__Guru**** 161600 points

Hello,

1 Have you considered the following recommendations from OMAP4470 TRM:

- the maximum size for each DDR supported is 1 GB.

The two EMIFs allow:
• Connection between the device and LPDDR2-SDRAM memories. Support two CSs per EMIF
controller.
• PHY is the DDR physical interface, which implements data-rate conversion in compliance with
LPDDR2 JEDEC requirements.
• Memory density up to 8 Gbits supported per CS. Total address space is limited to 2GB = 16 Gbits

2. Have you tried changing the memory settings in your x-loader (see http://e2e.ti.com/support/omap/f/849/t/233977.aspx) :
- In the x-loader, look at the struct defined in /cpu/omap4/sdram_elpida.c, which is assigned based on the OMAP type in the function __ddr_init(). You will need to change this to use the correct DDR struct (see the struct used for OMAP4470).

3. Micron are providing the following document, which describes the mobile ddr2 tuning (including thermal considerations): http://www.micron.com/~/media/Documents/Products/Technical%20Note/DRAM/tn4612.pdf

4. If you contact your TI representative, there is an application note available that describes LPDDR2 settings for OMAP in detail.

5 Regarding the FIFO underflow error I have discussed this issue in the following thread:

http://e2e.ti.com/support/omap/f/849/p/292061/1018379.aspx.
In summary you have to set DISPC_CONFIGo[16]BUFFERHANDCHECK

Best Regards,

Yordan

0 MihirShah over 11 years ago in reply to Yordan Kovachev

Prodigy 240 points

1. Yes, we considered two EMIF and two CS. Since the Micron part we used is 2x die package, we used CS1 as following,

2.Using the following same timings in xloader: sdram_elpdia.c

In mainline u-boot

static const struct lpddr2_ac_timings timings_elpida_400_mhz = {

.max_freq = 400000000,

.RL = 6,

.tRPab = 21,

.tRCD = 18,

.tWR = 15,

.tRASmin = 42,

.tRRD = 10,

.tWTRx2 = 7,

.tXSR = 140,

.tXPx2 = 7,

.tRFCab = 130,

.tRTPx2 = 7,

.tCKE = 3,

.tCKESR = 15,

.tZQCS = 90,

.tZQCL = 360,

.tZQINIT = 1000,

.tDQSCKMAXx2 = 5,

.tRASmax = 70,

.tFAW = 50

};

To use Ti release xloader

tried with all this ddr_regs structure

ddr_regs_elpida4G_400_mhz_1cs;(Works for REV-B3)

ddr_regs_elpida4G_466_mhz_1cs;

ddr_regs_elpida2G_400_mhz_2cs;

ddr_regs_elpida2G_400_mhz;(Works for REV-B3)

But using all the above structures, we are not able to boot the hardware at all. So we are using mainline u-boot.

Is there any other thing to be modfied to boot with TI release xloader.

3. The Micron pdf shows all data related power consumption..

4. We discussed with TI representative and asked for App note as well as Spreadsheet to calculate register settings for LPDDR2 timings...But they said, there no such things available for OMAP4..

5. We are already having fifohandcheck in same way

void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)

{

if (channel == OMAP_DSS_CHANNEL_LCD2)

REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);

else

REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);

}

Kindly let us know how do we move further?

Regards,

Mihir

0 MihirShah over 11 years ago in reply to MihirShah

Prodigy 240 points

Few more observations,

We had changed

.density = DDR_DENSITY_8Gb, to .density = DDR_DENSITY_4Gb,

The we see less flickering of ui and less heating. Please verify the timings once again which had been shared before.

Because of ram change we are having this issue in the same custom board with same build with different ram's

Regards,

Mihir

0 Yordan Kovachev over 11 years ago in reply to MihirShah

TI__Guru**** 161600 points

Hello,

According to Micron- MT42L256M32D2LK-18WT data sheet downloaded from: www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/Mobile%20DRAM/Low-Power%20DRAM/LPDDR2/U80M_4Gb_mobile_lpddr2_s4_sdram.pdf

The AC timings for data rate 1066 (533MHz) are:

tRPab (4-bank) = 18ns

tRPab (8-bank) = 21ns

tRCD = 18ns

tWR = 15ns

tRAS_MIN = 42ns

tRRD = 10ns

tWTR = 7.5ns

tXP = 7.5ns

tRTP = 7.5ns

tCKESR = 15ns

tDQSCK_MAX = 5500 ps

tFAW = 50ns

tZQCS = 90ns

tZQCL = 360 ns

tZQINIT = 1 us

tRAS_MAX = 70 us

tDQS_max_derated = 5620 ps

Regards,

Yordan

0 MihirShah over 11 years ago in reply to Yordan Kovachev

Prodigy 240 points

Thanks for timings details.

We checked all mentioned timings details in bootloader as well as kernel. Still the issue persists.

Following questions are open till date...Kindly help us on this front..

1. How to boot with TI release xloader? (checked with all the ddr registers in X-loader, but not able to boot it)

2. By using mainline u-boot weather there will be any problem of display arch? Since "FIFO UNDERFLOW on gfx, disabling the overlay" is coming.

If not why this comes and how to overcome this? This happens only micron ram and doesnt happen with elpdia ram with same Custom board and same build.

3. All the timings following seems to be correct checked with kernel timings and mainline u-boot also. Is there any more configurations or initialization need to be done for micron RAM MT42L256M32D2 ?

4. Weather xloader or bootloader ram configurations effects the kernel ram configurations?

5. Why the graphics problem comes. How we can over come this?

"omapdss DISPC error: FIFO UNDERFLOW on gfx, disabling the overlay omapdss DISPC error: mgr or device is NULL"

Checked the BUFFERHANDCHECK also as per your post.

0 MihirShah over 11 years ago in reply to MihirShah

Prodigy 240 points

We are doing memory speed test on both the memories their is a lot variations in results, below are the results

Micron Ram

memspeed_a9

size 8388608 8192k 8M

offset 8388608, 0

buffers 0x400c6000 0x408c6000

copy libc 159 MB/s

copy Android v5 175 MB/s

copy Android NEON 190 MB/s

copy INT32 126 MB/s

copy ASM ARM 172 MB/s

copy ASM ARM A9 177 MB/s

copy ASM VLDM 64 172 MB/s

read ASM ARM 352 MB/s

read ASM VLDM 345 MB/s

write libc 313 MB/s

write ASM ARM 333 MB/s

write ASM VSTM 323 MB/s

Elpdia Ram

memspeed_a9

size 8388608 8192k 8M

offset 8388608, 0

buffers 0x40031000 0x40831000

copy libc 294 MB/s

copy Android v5 309 MB/s

copy Android NEON 313 MB/s

copy INT32 280 MB/s

copy ASM ARM 307 MB/s

copy ASM ARM A9 309 MB/s

copy ASM VLDM 64 325 MB/s

read ASM ARM 542 MB/s

read ASM VLDM 498 MB/s

write libc 666 MB/s

write ASM ARM 717 MB/s

write ASM VSTM 714 MB/s

We see nearly half speed of operation in Micron memory even-though the timings are defined as per Micron datasheet...What can be the root cause here?

0 Yordan Kovachev over 11 years ago in reply to MihirShah

TI__Guru**** 161600 points

Hello,

I think this is because there is something not well defined in the settings of the micron chip.

Here is the procedure, when changing the lpddr2 chip:

1. Determining LPDDR2 Register Values

The first step in using a new LPDDR2 part with OMAP4 is to compute the values of the EMIF registers, with respect to the ddr geometry (size, width, number of chip selects, etc), and timings, by referencing the datasheet for the new LPDDR2 part.

2. Modifications in bootloaders (modifications to sdram_elpida.c)

The next step is to program the x-loader EMIF configuration to use the registers determined in 1). This configuration is done in the file /x-loader/cpu/omap4/sdram_elpida.c. This file contains structs of type ddr_regs for any of the LPDDR2 parts used with Blaze or Blaze Tablet. For example, the struct ddr_regs_elpida2G_400_mhz_2cs defines the Elpida EDB8064B1PB and is used by OMAP4430 ES2.3, OMAP4460 ES1.0, and OMAP4460 ES1.1 devices:

/*
* 400 MHz + 2 CS = 1 GB
*/
const struct ddr_regs ddr_regs_elpida2G_400_mhz_2cs = {
   /* tRRD changed from 10ns to 12.5ns because of the tFAW requirement*/
   .tim1       = 0x10eb0662,
   .tim2       = 0x20370dd2,
   .tim3       = 0x00b1c33f,
   .phy_ctrl_1   = 0x049FF408,
   .ref_ctrl   = 0x00000618,
   .config_init   = 0x80800eb9,
   .config_final   = 0x80801ab9,
   .zq_config   = 0xd00b3215,
   .mr1       = 0x83,
   .mr2       = 0x4
};

Check if sdram_elpida.c already includes a ddr_regs struct for the LPDDR2 device on your platform; otherwise, create a new struct in the same format but with values specific to the LPDDR2 device on your platform.

The entries in the ddr_regs struct correspond to the registers in the EMIF (see TRM, EMIF chapter) as follows:

tim1 SDRAM_TIM1

tim2 SDRAM_TIM2

tim3 SDRAM_TIM3

phy_ctrl_1 DDR_PHY_CTRL_1

ref_ctrl SDRAM_REF_CTRL

config_init SDRAM_CONFIG

config_final SDRAM_CONFIG

zq_config ZQ_CONFIG

The key values are config_init and config_final, which set the value of SDRAM_CONFIG before and after performing the rest of the SDRAM configuration. The difference between config_init and config_final is due to the read latency (RL) parameter. The boot begins with RL set to the default value of 3 (this and all following example values are for Elpida chips), which gives config_init = 0x80800EB9, in the example above. The LPDDR2 speed then changes to 466 MHz (RL=8) or to 400MHz (RL=6), as in the example above: config_final = 0x80801AB9.

The ddr_regs struct also sets the value for MR1 and MR2, which are mode registers programmed in the memory. You should consult JEDEC LPDDR2 specification for more detailed description of those registers.

Value for RL used in SDRAM_CONFIG must be programmed in MR2. For example, MR2 = 0x4 for RL = 6 (400MHz). 0x23 is the value for MR1 for DDR running at 200MHz, and 0x83 is the value for MR1 for DDR running any faster.

Update __ddr_init() function in sdram_elpida.c so that, for the correct OMAP44xx device type, the ddr_regs struct that was added for the new LPDDR2 part will be selected. ddr_init assigns the ddr_regs struct based on the OMAP44xx device.

Configure the LISA_MAP Register Values.

Have in mind that the default interleaving configuration for OMAP4430 ES2.0+, OMAP4460, and OMAP4470 is for
a 1GB LPDDR2. If a different LPDDR2 size is used, the DMM_LISA_MAP_3[22:20], which is the SYS_SIZE, should be configured to match the LPDDR2 size. SYS_SIZE = 0x5 indicates a 512MB section, 0x6 a 1GB section, and 0x7 a 2GB section. See the Dynamic Memory Management chapter in the TRM for more information.

3. As I said u-boot should not be modified. It uses the LPDDR settings as they are tuned in x-loader.

4. In kernel you should update the board file accordingly. Update the all emif settings as per your case, with regards to the lpddr chip you are using.

Best Regards,

Yordan

0 Eason Wang over 11 years ago in reply to Yordan Kovachev

TI__Genius 13460 points

Hi Yordan,

My customer want to use Elpida DDR type EDB8164B3PF-1D-F-D to replace samsung K3PE7E700M-XGC1.

It is quite clear in kernel to configurate the EMIF registers, but in x-loader, except timing registers, others need to be caculated, which we are not quite clear.

Could you advise if there is an example or caculation sheet we can follow?

Thanks & Best Regards,

Eason

0 Yordan Kovachev over 11 years ago in reply to Eason Wang

TI__Guru**** 161600 points

Hello Eason,

There is a guide for configuring x-loader, when changing the DDR chip on your board, but it is under NDA and I cannot discuss it in a public forum.

Best Regards,

Yordan

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Issue with Micron- MT42L256M32D2LK-18WTA - LPDDR2 on OMAP4470