how to enable the DSP C64x+ clock using CCS and Windows Operating System on OMAP3503EVM

You would have to modify the GEL file to configure the clocks for a 430MHz C64x+, unfortunately I have not seen such a GEL file myself, I am checking internally to see if one exists, otherwise the GEL file would have to be modified by hand.

In gel files I received from LogicPd for their 3530 Zoom board  I found that the GEMStartup routine was putting the IVA DPLL in bypass so it was running at the core clock speed. I had to modify the files.

In General there seems to be quite confusing documentation on the clocks.  Spruf98  implies a max clock of 360Mhz in table 1-6.  But I have been told 500 is max, and have gel file from LogicPd for 499.2M.   which is it?

I have a question about the clock configuration.  Spruf98 says in 4.7.2.1.2  that when the external clock is 26M or 38M, it is divided intermally to make the 13 or 19.2.   But it does not say who is resposible for doing that, or if it is even required.   Figure 4-38 shows a divider in the SYS_CLK path but no mention of controlling register.

  There are two registers:

PRM_CLKSEL where you tell it the external clock speed,  but spruf98 doesnt say how thats used.   and

PRM_CLKSRC_CTRL  where in bits 6-7 you can specify a division of the internal clock to take place ahead of routing to DPLLs.

My question is :   when the external clock is 26M  is the divide by 2 automative by way of setting PRM_CLKSEL?   Or am I required to set PRM_CLKSRC_CTRL[7:6] explicitly to achieve this?   If the latter,  what happens if I do not divide?

Take a look at SPRS507C, Table 4-16: DPLL2 Clock Frequency Ranges:

430 MHz maximum is for OPP5 Overdrive operating mode, and 360 MHz maximum is for OPP3 Normal operating mode.

I would not recommend to set it to the maximum Overdrive mode operating frequency (430 MHz) because the device will dissipate more heat and this might shorten the life of the device. 

What I know from reading SPRUFA5B, IVA2 clock is derived from two sources: DPLL2_ALWON_FCLK and DPLL2_FCLK. 

In the bypass mode, IVA_CLK is a factor of  the CORE_CLK depending on the CM_CLKSEL1_PLL_IVA2[21:19] IVA2_CLK_SRC value. 

In the lock mode, the DPLL2_ALWON_FCLK is feeded to a prescaler (IVA2_DPLL_MULT & IVA2_DPLL_DIV) and a clock divider (IVA2_DPLL_CLKOUT_DIV) and generate the IVA_CLK output.

In your case, the DPLL2_ALWON_FCLK is the 26 MHz oscillator clock divided by 2 if the PRM_CLKSEL[2:0] OSC_ SYS_CLK = 0x00000003, and PRM_CLKSRC_CTRL[7:6] SYSCLKDIV = 2

So, to set the DPLL2 in lock mode and outputing 360 MHz  IVA_CLK. Set CM_CLKSEL1_PLL_IVA2 = 0x0009680C, and CM_CLKSEL2_PLL_IVA2 = 0x00000001.

If you are running Linux 2.6.28  on the ARM side, you can modify the OMAP Linux board support package to generate the 360 MHz IVA2 clock. Below is the patch file:

diff -BurN linux-2.6.28-rc8/arch/arm/mach-omap2/clock34xx.h linux-2.6.28-rc8.mod/arch/arm/mach-omap2/clock34xx.h
--- linux-2.6.28-rc8/arch/arm/mach-omap2/clock34xx.h    2009-11-30 22:09:38.000000000 -0500
+++ linux-2.6.28-rc8.mod/arch/arm/mach-omap2/clock34xx.h        2009-11-30 16:29:45.000000000 -0500
@@ -382,7 +382,7 @@
        .parent         = &sys_ck,
        .prcm_mod       = OMAP3430_IVA2_MOD,
        .dpll_data      = &dpll2_dd,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
        .enable         = &omap3_noncore_dpll_enable,
        .disable        = &omap3_noncore_dpll_disable,
        .round_rate     = &omap2_dpll_round_rate,
diff -BurN linux-2.6.28-rc8/arch/arm/mach-omap2/pm34xx.c linux-2.6.28-rc8.mod/arch/arm/mach-omap2/pm34xx.c
--- linux-2.6.28-rc8/arch/arm/mach-omap2/pm34xx.c       2009-11-30 22:09:36.000000000 -0500
+++ linux-2.6.28-rc8.mod/arch/arm/mach-omap2/pm34xx.c   2009-11-30 17:41:02.000000000 -0500
@@ -638,6 +638,7 @@
 static void __init omap3_iva_idle(void)
 {
        struct clk *iva2_ck, *dpll2_ck;
+       u32 v;

        iva2_ck = clk_get(NULL, "iva2_ck");
        if (!iva2_ck) {
@@ -663,7 +664,14 @@

        /* FIXME: DPLL2 init to be removed when DPLL init and M, N preserve
         *        patches are in */
-       clk_set_rate(dpll2_ck, 125000000);
+       /* Ctran - set the IVA2 clock rate to maximum allowable for OOP3 */
+       clk_set_rate(dpll2_ck, 360000000);
+
+       /* Ctran - enable IVA2 DPLL in lock mode */
+       v = cm_read_mod_reg(dpll2_ck->prcm_mod, dpll2_ck->dpll_data->control_reg);
+       v &= ~dpll2_ck->dpll_data->enable_mask;
+       v |= 0x7 << __ffs(dpll2_ck->dpll_data->enable_mask);
+       cm_write_mod_reg(v, dpll2_ck->prcm_mod, dpll2_ck->dpll_data->control_reg);

        /* Enable IVA2 clock */
        clk_enable(iva2_ck);

thanks Chi

I will look at those docs. i have been told by our local rep that 550Mhz is achievable.

Anyway, so to re-iterate,  does using  26MHz 'reguire' that PRM_CLKSRC_CTRL[7:6] SYSCLKDIV = 2?   And if so, i would assume you must use 13Mhz in the setup equations for the DPLL.

The code I have is not setting divide by 2, it is divide by 1, and DPLL setup math is using 26M.   But we have doubts of the actual speed we are running.

Using the 26 MHz does not require PRM_CLKSRC_CTRL[7:6] SYSCLKDIV = 2. But then your system clock (SYS_CLK) will be 26 MHz instead of 13 MHz. The SYS_CLK also drives many other clocks. Refer to Figure 1-38 PRM Clock Generator.

Yes, I was using the 13 MHz in the setup equations for the DPLL.