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about am335x latch-up current

Ruiming Feng
Prodigy 50 points

I want to know, why am335x some pin latch-up current  is 45mA?

Is this a bug about the CPU? The latch-up current is so small, what's fluence?

  • 0
    TI__Guru 64305 points

    As internal geometries decrease with advanced semiconductor process technologies, it has become more difficult to meet latch-up limits that have been recognized as industry standard limits for many years.

    Previous revisions of JEDEC standard JESD78 defined specific limits for latch-up testing, but these limits were removed beginning with revision "D".

    The latch-up performance parameter published in the AM335x Data Sheet represents the worst case value for Class II operating conditions.  Also characterization results have shown it is not possible to inject enough current to cause latch-up if the voltage applied to terminals do not exceed the Transient Overshoot and Undershoot limit defined in the AM335x Data Sheet.

    Regards,
    Paul

  • 0 in reply to peaves
    Prodigy 50 points

    As internal geometries decrease with advanced semiconductor process technologies, it has become more difficult to meet latch-up limits that have been recognized as industry standard limits for many years.

    From this sentence, could I think this is a bug of the CPU? Because I find other company chip can meet 100mA latch-up current limits. For example Freescale.

    Could you tell me where could find Transient Overshoot and Undershoot limit defined in the AM335X Data Sheet?

  • 0 in reply to Ruiming Feng
    TI__Guru 64305 points

    We do not consider the latch-up performance value published in the AM335x Data Sheet a bug.

    The value is lower that what has been used for many years, but the old limit may be much larger than required by most applications.  There has not been any reports of this limit causing an issue.

    The "Transient Overshoot and Undershoot Specification at IO Terminal" is the third parameter above the "Latch-up Performance" parameter, in the same table.

    Regards,
    Paul 

  • 0 in reply to peaves
    Prodigy 50 points

    I want to konw when you define latch-up current limit, why do you define so small?

    I feel this value is too small, I couldn't understand your design idea.

    I read JESD78D file, find that you select  <50mA class.  I want to know why?

  • 0 in reply to Ruiming Feng
    TI__Guru 64305 points

    The latch-up performance published in the AM335x Data Sheet represents actual worst case limits of all IOs.  The published value does not represent the design goal.  We do not publish or discuss design goals in a public forum.

    Do you have a specific example where a system could produce more than 45mA of current into an IO while maintaining the Transient Overshoot and Undershoot limits defined in the AM335x Data Sheet?

    Regards,
    Paul