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EDMA3 alignment restrictions

Yossi Regev
Prodigy 220 points

Hello

I work with TMS320C6657 EVM, with CCS5.4, SYS/BIOS 6.35 and c6000_7.4.2 compiler.

I read in "KeyStone Architecture. Enhanced Direct Memory Access (EDMA3) Controller" document that "For SAM in increment mode, there are no alignment restrictions imposed by EDMA3" (2.3.2.2 Channel Source Address).

When I try to copy from DDR3 memory with EDMA3 I see that the first bytes are not copied unless the address in DDR3 is alignment to 64 Bytes address. (s.t. address that is multiple of 0x40).

Are there such restrictions?

Are these restrictions tied to the Default Burst Size (DBS=64 in C6657)?

Is there option to change the Default Burst Size (DBS)?

 

Thank you

Yossi Regev