• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 98 subscribers
  • Views 1051 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

EDID read failed HDMI

selvam mk
Intellectual 970 points

Hi all,

I'm using kernel PSP (04.04.00.02)release with dm38x, and while loading hdmi driver i'm getting the following error log.

" I2C Bus Low? HDMI failed to read E-EDID"

[   14.100000] HDMI W1 rev 4.0
[   14.110000] HDMI CEC Spec version 1.2
[   14.130000] PM: Adding info for No Bus:TI81XX_HDMI
[   14.140000] hdmi: Enter HDMI_W1_StopVideoFrame()
[   14.140000] hdmi: *** Set PHY power mode to 1
[   14.140000] hdmi: *** Set PHY power mode to 2
[   14.500000] I2C Bus Low?
[   14.500000]
[   14.500000] HDMI failed to read E-EDID
[   14.500000] hdmi: Enter HDMI_W1_GlobalInitVars()
[   14.850000] hdmi: Enter HDMI_Core_GlobalInitVars()
[   14.960000] hdmi: Enter HDMI_W1_ConfigVideoResolutionTiming()
[   14.960000] hdmi: Enter HDMI_W1_ConfigVideoInterface()
[   14.960000] hdmi: Enter DSS_HDMI_CORE_SW_RESET_ASSERT ()
[   14.960000] hdmi: Enter DSS_HDMI_CORE_POWER_DOWN_DISABLE()
[   14.960000] hdmi: Enter DSS_HDMI_CORE_SW_RESET_RELEASE()
[   14.960000] hdmi: Enter HDMI_W1_StartVideoFrame  ()
[   14.960000] hdmi: Irqenable 60000011
[   14.960000] hdmi: 40 hpd

From the code its checking the 6th bit of DDC_STATUS what is the base address of the register.?


what could be the problem, my hdmi sda & clk are pulled high.

Regards,

Manoj

  • 0
    TI__Guru**** 170625 points

    Hi Manoj,

    selvam mk said:

    I'm using kernel PSP (04.04.00.02)release with dm38x, and while loading hdmi driver i'm getting the following error log.

    " I2C Bus Low? HDMI failed to read E-EDID"

    I am not familiar with DM38x device, I work with DM814x/AM387x. Do you have on-chip HDMI on DM38x device? Refer to the below e2e thread for info:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/295516.aspx

    selvam mk said:
    From the code its checking the 6th bit of DDC_STATUS what is the base address of the register.?

    In DM814x/AM387x, the base address is provided in the datasheet, while the register offset is provided in the TRM. I assume this will be the same with DM38x device.

    Best regards,
    Pavel