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Configure Timers

JoaoPauloB
Prodigy 30 points
Other Parts Discussed in Thread: OMAP3530

Hi,

I am newbie and i am working with OMAP3530 processor. I am trying to configure the timer 2 to be interrupted each 5 ms. But without successfully. Does anyone could help me in set up the timer registers? I am not familiarized with timers.

    outl(0x0300, TIOCP_CFG); /* clock activity */
    outl(0x0001, TIER_GPT2); /* enable match interrupt */
    outl(0x00EC, TMAR_GPT2);
    outl(0x0041,  TCLR_GPT2); /* start timer - compare enable */

 

Is the configuration correct? missing any register?

Thanks,

João Paulo

  • 0
    TI__Guru 64570 points

    As I understand your requirements, you would like to configure the General Purpose Timer 2 (GPTimer2) to generate an interrupt every 5 msec, correct?

    After you perform the above configuration writes, if you read the TCRR, is this changing?
    The other item to look for is the TISR.MAT_IT_FLAG, bit[0] of TISR register to see if the match interrupt flag is getting set.  It may not be propagating through to the CPU, but might still be firing.

     

  • 0
    TI__Mastermind 41665 points

    As a bit of an alternative method, I am curious if you are trying to do this from the ARM or the DSP, and if you are using Linux or DSP/BIOS? As opposed to setting up a timer manually like this you may want to consider using your OSes services, such as the timing capabilities of Linux or the PRD functionality of DSP/BIOS. Using these existing software structures will take care of configuring the timer and interrupts for you.

  • 0 in reply to BrandonAzbell
    Prodigy 30 points

    Hi Bernie and Brandon.

     

    Thanks for your reply. The timer is working now, i can see my printk function when the TCRR (counter) match TMAR :)

    But there is just one issue, the TCRR is not reseting (going to zero) when match with TMAR, i am doing this in the isr function (writing 0 to TCRR) but this is not right.

    Which register should i set to TCRR going to zero every time that match with TMAR?

     

    Regards,

    João Paulo

  • 0 in reply to JoaoPauloB
    TI__Guru 64570 points

    JoaoPauloB said:

    But there is just one issue, the TCRR is not reseting (going to zero) when match with TMAR, i am doing this in the isr function (writing 0 to TCRR) but this is not right.

    Which register should i set to TCRR going to zero every time that match with TMAR?


    Do you have the timer setup for a one-shot mode, or auto-reload?  If one-shot mode, the timer may trigger the interrupt upon matching TMAR, but leave the contents of TCRR intact.
    If you set the TCLR.AR, bit 1, to 0x1, this would configure the timer to automatically reload the TCRR with the contents of TLDR.  This is described in Section 16.2.4.2 of the TRM.

     

     

  • 0 in reply to BrandonAzbell
    Prodigy 30 points

    Hi Brandon,

    So it's strange, because i am setting as auto-reload mode. When TCRR match TMAR, the TCRR doesn't reload with the contents of TLDR.

    Below i show the configurations of the registers. Are there any issues in my registers configurations?

     

    OCP: 0x210
    TMAT: 0x7e02
    TLDR:  0x1
    TCLR: 0x43 // auto-reload mode
    TIER: 0x1

     

    Regards,

    João Paulo

  • 0 in reply to JoaoPauloB
    Prodigy 170 points

    I had a similiar timer issue. I changed a bunch of things but the one I believe really fixed the problem was using the posted mode.