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UART interrupts not working as expected

fxrb
Intellectual 440 points
Other Parts Discussed in Thread: AM3352

Hello,

If THRIT in IER and and TXEMPTYCTLIT in SCR are set, according to the TRM table 19-58 the following should happen: "THR interrupt is generated when TX FIFO and TX shift register are empty", i.e. there is no more bit to be transferred, correct?

If a test for "(lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI)"  in the interrupt routine is true, then there is no more bit to be transferred, i.e. the last bit has left the shift register, correct?

In a test application I send 5 bytes through an RS-485 transceiver with 9600 bps. When the condition described above is met in the interrupt handler I disable the RS-485 transceiver so no more bits can leave it. From the 5 bytes I send I can only receive 3 on the other side of the transceiver. It looks like I am disabling the transceiver too early, but what I am doing is in accordance with the TRM, I think.

What am I missing in the configuration of the interrupts?

Many thanks and kind regards, Felix

  • 0
    TI__Guru**** 393215 points
    Hi Felix,
     
    What is the processor, the TRM revision and the software being used?
  • 0 in reply to Biser Gatchev-XID
    Intellectual 440 points

    Hello Biser,

    Sorry for not supplying this information in my first post:

    SOC: AM3352
    TRM: version SPRUH73H

    The system is running LINUX from the TI SDK so I am referring to 'omap-serial'. My test-software is a simple C program writing the 5 bytes to the UART. The switching of the the transceiver is done by toggling the RTS line. This is directly implemented in the interrupt routing of 'omap-serial' (for testing).

    regards Felix

  • 0 in reply to fxrb
    TI__Guru**** 393215 points
    Make sure you always have the latest TRM version. Current is Rev. I. On your question:
     
    The LSR register bit 6, TXSRE is set to 1 when both the THR (or FIFO if it's enabled) and the transmit shift register are empty. I'm not sure about the SCR TXEMPTYCTLIT bit behaviour - I seem to remember that other people also had problems with this.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 440 points

    Hello Biser,

    Thanks, I am now up to date with the TRM. In fact I was referring to bit TXSRE in register LSR when talking about UART_LSR_THRE (which is a defined that equals to 0x20). I hope that the TXEMPTYCTLIT in SCR is working according to the TRM.

    For the TXSRE bit in the LSR, this might be a software glitch. I will try to further research this and eventually get back with some additional information.

    many thanks and kind regards, Felix

  • 0 in reply to fxrb
    TI__Guru**** 393215 points
    It should be 0x40 for TXSRE bit, not 0x20. I have confirmation from the factory team that  TXEMPTYCTLIT in SCR is working as described in the TRM.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 440 points

    Hello Biser,

    Oh no, I just used the wrong define!
    From 'serial_reg.h' I used UART_LSR_THRE which is wrong, the correct one is UART_LSR_TEMT.

    Thanks a lot that hint, regards, Felix