OMAP35x interface to Mobile DDR

I believe what you are looking for is within section 6.4.2 of the OMAP35x datasheet, this section outlines design guidelines to help you layout your board such that your DDR interface meets the timing requirements of the DDR peripheral. If you have done prior DDR layouts with TI processors this is roughly the equivalent of what would be in a DDR layout application note, it has simply been moved to within the datasheet instead of a seperate document. The application note here provides a discussion on why TI does their DDR specification this way and how this should make your layout experience easier and more likely to succeed.

Thank you, I knew that I had seen some information somewhere, but was looking in the Technical Reference Manual.