• Locked Locked
  • Replies 1 reply
  • Subscribers 99 subscribers
  • Views 410 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

OMAP35xx L3 interconnect

mohamed2351
Prodigy 30 points

Hi all,

In the OMAP 35xx technical manual, it neither specifies the minimum latency for L3 interconnect nor how to estimate it. I am trying to evaluate the architecture for future project work and I want to develop an estimation of the cache miss penalty.

 

Any help is highly appreciated.

 

Best Regards,

Mohamed

  • TI__Mastermind 41665 points

    Unfortunately I do not think we have figures for that (if anyone has any please correct me), but I would not be suprised to see a bandwidth application note come out some day as some of our other devices have them.

    For now I would say that the L3 is relatively fast, so for cache miss calculations, the bulk of the delay will be the actual external memory access as opposed to any latency added on by the L3 interconnect. So for a cache miss, the time to initiate and complete a DDR access should be fairly close to the amount of time you would see in a cache miss assuming you are accessing a DDR location.