How to distinguish the concept between MMU ,PAE and XMC on tci6638k2k

You are right, the MMU translates logical memory (32 bits) into physical memory (40 bits) when the ARM access the memory.

On the DSP and other masters on the Teranet bus, the translation is done by the MPAX registers. For the DSP cores, MPAX registers that are part of the XMC translate 32 bit logical into 36 physical address.  Please do not be confused between the 36 bots and the 40 bits since the upper 4 bits of the 40 bits are always zero.  Similar sets of registers tranlate logical 32-bit to physical 36-bit for all other masters in the device when other masters access through the TeraNet. (other masters means any IP or peripheral that can be master on the bus, that is, can put a request on the bus like the SRIO when it writes to memory)

Both, the MMU and the MPAX translate logical to physical, but they have different features:

1. MMU for ARM, MPAX for DSP cores and other masters

2. MMU manages teh memory dynamically, MPAX are static (that is, you configure the translation and unless you change the configuration, this is a fixed translation.  MMU assigns pages to process and free them when teh process terminates). Without getting into more details,  MMU is a generic module and you have lot's of information how it works, MPAX reisters have limited functionality - just static translation and protection.

To understand bette how the translation works, look at table 6-1 of http://www.ti.com/lit/ug/sprugw0c/sprugw0c.pdf  and especailly at the end of the table and reads the comments. See the ARM view of memory and the DSP view of the memory, and see that the upper 4 bits (this is the difference between 40 bits and 36 bits) are always zero

Ran

Ran:

thanks for your reply.

Why you considered that the 32bit address was logical address and 36bit address or 40bit address

was physical address?

In my opinion,I always believed that the size of logical memory space should be more larger than the size of

of physical memory space.

But now you said that 32bit address was logical and 36bit or 40bit was physical .It mean that

logical memory space was smaller than physical memory space.Maybe something wrong.I had time to

looked into the point.

Steve

I do not consider that 32bit is logical and 36 (or 40) is physical.  This is how it is in the keyStone family devices

If you ask me what were the considerations of the designers when they decided to build KeyStone devices,  I can assure you that they had reasons. 

The core registers are 32 bit and so is the internal device address bus. if one wants to enable larger physical  memory than 4G (which is 32 bit address), one must have more bits for the physical memory. This enables (for example, there are many other posibilities) assigning 1G of external memory to each core.

We explain all these type of considerations in a workshop that we give in different places.  It might be a good idea for you to join one of these workshops and learn

Best regards

Ran 

hi Ran:

I don't quite follow you.

Would you agree or not agree with that 32bit is a logical address and

36bit or 40bit is physical?

I heard that you couldn't agree with that but it was true in the keystone family devices.

Didn't it?

 KeyStone devices of Texas Instrument support 32 bit logical address and 36 or 40 physical addresses

Let me repeat

KeyStone devices of Texas Instrument support 32 bit logical address and 36 or 40 physical addresses

If you use other devices, I cannot answer. Do you use other device? Of other manufactures?  Please ask them

What is that you do not understand?  How can I help you understanding?

Ran

Ran:

I understand your meaning.

Your meaning is that it is wright for Keystone devices considering 32bit as logical address and 40bit

as physical address even it is not very popular and not very usually .

Thank again.

Yes, you are correct

Best Regards

Ran