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AM335X GPMC Timing diagram is very stange

Hi  everybody

    I configue GPMC as 16bit non-mux norflash mode,but the GPMC timing is very strange, 

the cs and we or oe is like follow:

read timing, cs and oe

write: cs and wr

  • the configuration is as followed:

    and I changed the timing many times, the gpmc timing is still as the picture above!!

    static struct gpmc_timings fpga_timings =
    {
    .sync_clk = 0,

    .cs_on = 0,
    .cs_rd_off = 80,
    .cs_wr_off = 80,

    .we_on = 40,
    .we_off =58,

    .oe_on = 40,
    .oe_off = 60,
    .access = 70,
    .rd_cycle = 81,
    .wr_cycle = 81,
    };

    gpmc_cs_write_reg(GPMC_CS, GPMC_CS_CONFIG1, GPMC_CONFIG1_READTYPE_ASYNC |
    GPMC_CONFIG1_WRITETYPE_ASYNC |
    GPMC_CONFIG1_DEVICESIZE_16 |
    GPMC_CONFIG1_DEVICETYPE_NOR |
    GPMC_CONFIG1_FCLK_DIV3);

    val = gpmc_cs_read_reg(GPMC_CS, GPMC_CS_CONFIG1);
    val &= NONE_MUXADDATA;
    gpmc_cs_write_reg(GPMC_CS, GPMC_CS_CONFIG1, val);

  • What are you trying to achieve? Can you give more details?