DM8168 Decoding External Display

yuxi

I want to complete external display by PCIe port after decoding.

Now the output of swms link should be the mapping address of the PCIe port, and the following link of the swms link is NULL link, instead of the display link.

There are some questions about the PCIe port:

1.What should be the mapping address of PCIe? In DVR_RDK4.0, How could I get it? Could you explain which files are involved in PCIe port physical and virtual mapping address?

2. Could M3 access the address of PCIe mapping address directly? What's the differences between the M3 and A8 access of the PCIe address?

Thanks.

over 12 years ago

0 Badri Narayanan over 12 years ago

TI__Guru 59700 points

For PCIe driver details refer :

http://processors.wiki.ti.com/index.php/TI81XX_PSP_PCI_Express_Endpoint_Driver_User_Guide

M3 cannot access PCIe registers. You need to use ipcFramesOut (M3VPSS) -> ipcFramesIn (A8) link connection to get the decode output to A8 and then transfer the frames via PCIe.

0 yuxi over 12 years ago in reply to Badri Narayanan

Intellectual 650 points

Thanks for your valuable help.

I need to scale the frames for the display, and I use 2 swms and then merge them to the ipcFramesOut (M3VPSS) -> ipcFramesIn (A8) link connection.

The configuration code is as follows:

    for (channelNum = 0; channelNum < CHAINS_SW_MS_MAX_DISPLAYS; channelNum++)
   {
    swMsPrm[channelNum].numSwMsInst      = 1;
    swMsPrm[channelNum].inQueParams.prevLinkId   = dupId;
    swMsPrm[channelNum].inQueParams.prevLinkQueId = channelNum;
    swMsPrm[channelNum].swMsInstId[0] = SYSTEM_SW_MS_SC_INST_VIP1_SC;
    swMsPrm[channelNum].outQueParams.nextLink = mergeId;
    swMsPrm[channelNum].lineSkipMode    = FALSE;
    swMsPrm[channelNum].enableLayoutGridDraw = FALSE;
    swMsPrm[channelNum].layoutPrm.outputFPS = DEFAULT_FRAME_RATE;
    swMsPrm[channelNum].maxInputQueLen    = SYSTEM_SW_MS_DEFAULT_INPUT_QUE_LEN;
    swMsPrm[channelNum].maxOutRes     = displayRes[channelNum];
    swMsPrm[channelNum].numOutBuf     = 0;
    swMsLayout1x1Params(&layout_id[0], &swMsPrm[channelNum]);
   }

   mergePrm.numInQue                      = 2;
   mergePrm.inQueParams[0].prevLinkId     = swMsId[0];
   mergePrm.inQueParams[0].prevLinkQueId = 0;
   mergePrm.inQueParams[1].prevLinkId     = swMsId[1];
   mergePrm.inQueParams[1].prevLinkQueId = 0;
   mergePrm.outQueParams.nextLink         = ipcFramesOutVpssToHost;
   mergePrm.notifyNextLink                = TRUE;

   ipcFramesOutVpssToHostPrm.baseCreateParams.inQueParams.prevLinkId = mergeId;
   ipcFramesOutVpssToHostPrm.baseCreateParams.noNotifyMode = FALSE;
   ipcFramesOutVpssToHostPrm.baseCreateParams.notifyNextLink = TRUE;
   ipcFramesOutVpssToHostPrm.baseCreateParams.notifyPrevLink = FALSE;
   ipcFramesOutVpssToHostPrm.baseCreateParams.inQueParams.prevLinkQueId = 0;
   ipcFramesOutVpssToHostPrm.baseCreateParams.outQueParams[0].nextLink = ipcFramesInA8Id;
   ipcFramesOutVpssToHostPrm.baseCreateParams.inputFrameRate = DEFAULT_FRAME_RATE;
   ipcFramesOutVpssToHostPrm.baseCreateParams.outputFrameRate = DEFAULT_FRAME_RATE;
   ipcFramesOutVpssToHostPrm.baseCreateParams.notifyProcessLink = FALSE;

   ipcFramesInHostPrm.baseCreateParams.noNotifyMode = TRUE;
   ipcFramesInHostPrm.baseCreateParams.notifyNextLink = FALSE;
   ipcFramesInHostPrm.baseCreateParams.notifyPrevLink = FALSE;
   ipcFramesInHostPrm.baseCreateParams.inQueParams.prevLinkId = ipcFramesOutVpssToHost;
   ipcFramesInHostPrm.baseCreateParams.inQueParams.prevLinkQueId = 0;
   ipcFramesInHostPrm.baseCreateParams.outQueParams[0].nextLink = SYSTEM_LINK_ID_INVALID
   ipcFramesInHostPrm.exportOnlyPhyAddr = FALSE;
   ipcFramesInHostPrm.baseCreateParams.inputFrameRate =DEFAULT_FRAME_RATE;
   ipcFramesInHostPrm.baseCreateParams.outputFrameRate = DEFAULT_FRAME_RATE;
   ipcFramesInHostPrm.baseCreateParams.notifyProcessLink = FALSE;
   Chains_ipcFramesInSetCbInfo(&ipcFramesInHostPrm);

But there is an error in the running result as follows:

848:!!!SLAVE CORE [VPSS-M3] DOWN!!!
SystemLink_copySlaveCoreExceptionContext:120
mmap of [0xbe9e0000:36864]
mmap virt addresss:0x4006a000
munmap of [0x4006a000:36864]
SystemLink_copySlaveCoreExceptionContext:127

Then I delete the merge link, and modify the 2 swms link following with 2 ipcFramesOut (M3VPSS) and 2 ipcFramesIn (A8) link, it runs OK.

So what's the bug in merge link? and could swms link follow with merge link?

0 Badri Narayanan over 12 years ago in reply to yuxi

TI__Guru 59700 points

Below code is wrong.

  ipcFramesOutVpssToHostPrm.baseCreateParams.noNotifyMode = FALSE;
   ipcFramesOutVpssToHostPrm.baseCreateParams.notifyNextLink = TRUE;
   ipcFramesOutVpssToHostPrm.baseCreateParams.notifyPrevLink = FALSE;

It should be

  ipcFramesOutVpssToHostPrm.baseCreateParams.noNotifyMode = TRUE;
   ipcFramesOutVpssToHostPrm.baseCreateParams.notifyNextLink = FALSE;
   ipcFramesOutVpssToHostPrm.baseCreateParams.notifyPrevLink = TRUE;

Share the full assert log. Make sure you are creating links in sequence correctly

SwMs,merge,ipcFramesOutVpss,ipcFramesInHost

0 yuxi over 12 years ago in reply to Badri Narayanan

Intellectual 650 points

Thanks for your timely reply！I have solved the problem with your help.

But there is another problem coming out. I modified the memory map as follows(in /mcfw/src_bios6/cfg/ti816x/config_2G.bld):

/* first 512MB */
LINUX_SIZE                 = 256*MB;
SR1_SIZE                   = 208.5*MB;
SR3_INTRADUCATI_IPC_SIZE   = 124*KB;
VIDEO_M3_CODE_SIZE         = 2.5*MB;
VIDEO_M3_DATA_SIZE         = 12*MB;
DSS_M3_CODE_SIZE           = 1.5*MB;
DSS_M3_DATA_SIZE           = 17*MB;
DSP_CODE_SIZE              = 900*KB;
DSP_DATA_SIZE              = 13.5*MB;

TILER_SIZE = 1024*MB;

SR2_FRAME_BUFFER_SIZE      = 490*MB - 256*KB;
SR0_SIZE                   = 15*MB;
VIDEO_M3_EXCEPTION_CTX_SIZE = 128*KB;
VPSS_M3_EXCEPTION_CTX_SIZE = 128*KB;
HDVPSS_DESC_SIZE           = 2*MB;
HDVPSS_SHARED_SIZE         = 2*MB;
NOTIFY_SHARED_SIZE         = 2*MB;
REMOTE_DEBUG_SIZE          = 1*MB;

LINUX_ADDR                 = DDR3_ADDR;
SR1_ADDR                   = LINUX_ADDR                 + LINUX_SIZE;
SR3_INTRADUCATI_IPC_ADDR   = SR1_ADDR                   + SR1_SIZE;
VIDEO_M3_CODE_ADDR         = SR3_INTRADUCATI_IPC_ADDR   + SR3_INTRADUCATI_IPC_SIZE;
VIDEO_M3_DATA_ADDR         = VIDEO_M3_CODE_ADDR         + VIDEO_M3_CODE_SIZE;
DSS_M3_CODE_ADDR           = VIDEO_M3_DATA_ADDR         + VIDEO_M3_DATA_SIZE;
DSS_M3_DATA_ADDR           = DSS_M3_CODE_ADDR           + DSS_M3_CODE_SIZE;
DSP_CODE_ADDR              = DSS_M3_DATA_ADDR           + DSS_M3_DATA_SIZE;
DSP_DATA_ADDR              = DSP_CODE_ADDR              + DSP_CODE_SIZE;

TILER_ADDR = DSP_DATA_ADDR + DSP_DATA_SIZE

SR2_FRAME_BUFFER_ADDR       = DDR3_ADDR + 1536 * MB;
VIDEO_M3_EXCEPTION_CTX_ADDR = SR2_FRAME_BUFFER_ADDR     + SR2_FRAME_BUFFER_SIZE;
VPSS_M3_EXCEPTION_CTX_ADDR = VIDEO_M3_EXCEPTION_CTX_ADDR + VIDEO_M3_EXCEPTION_CTX_SIZE;
HDVPSS_DESC_ADDR           = VPSS_M3_EXCEPTION_CTX_ADDR   + VPSS_M3_EXCEPTION_CTX_SIZE;
HDVPSS_SHARED_ADDR         = HDVPSS_DESC_ADDR           + HDVPSS_DESC_SIZE;
NOTIFY_SHARED_ADDR         = HDVPSS_SHARED_ADDR         + HDVPSS_SHARED_SIZE;
REMOTE_DEBUG_ADDR          = NOTIFY_SHARED_ADDR         + NOTIFY_SHARED_SIZE;
SR0_ADDR                   = REMOTE_DEBUG_ADDR         + REMOTE_DEBUG_SIZE;

and modified the argboots:

setenv bootargs 'mem=256M console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=***.**.**.***:/home/workdir/DM8168/target/rfs_816x,nolock ip=***.**.***.***:***.**.**.***:***.**.**.1:255.255.255.0:xxxx:eth0:off vram=20M notifyk.vpssm3_sva=0xFEE00000'

The program runs in death. The result：

*** Bootargs Validated for mem param ***
*** Bootargs Validated for notifyk.vpssm3 params ***
Kernel bootargs validated
numid=1,iface=MIXER,name='PCM Playback Volume'
; type=INTEGER,access=rw---R--,values=2,min=0,max=127,step=0
: values=127,127
| dBscale-min=-63.50dB,step=0.50dB,mute=0
[c6xdsp ] Remote Debug Shared Memory @ 0xff000000
[m3video] Remote Debug Shared Memory @ 0xff005020
[m3vpss ] Remote Debug Shared Memory @ 0xff00a040
SysLink version : 2.10.02.17
SysLink module created on Date:Oct 15 2013 Time:15:11:31
Trace enabled
Trace SetFailureReason enabled
Setting DMM priority for [DUCATI ] to [0] ( 0x4e000624 = 0x08000000 )
Setting DMM priority for [HDVICP0 ] to [2] ( 0x4e000634 = 0x0000000a )
Setting DMM priority for [HDVICP1 ] to [2] ( 0x4e000634 = 0x000a0000 )
Setting DMM priority for [HDVICP2 ] to [2] ( 0x4e000634 = 0x00a00000 )
Attached to slave procId 2.
Loaded file ../firmware/dvr_rdk_fw_m3vpss.xem3 on slave procId 2.
Started slave procId 2.
After Ipc_loadcallback status [0x00000000]

and then in death.

I think the reason for the bug is that notifyk.vpssm3_sva is configured in error

or what needs to be modified with the NOTIFY_SHARED_ADDR modified.

Is it right? and How could I correct the errors?

Looking forwards to your replying!

0 Badri Narayanan over 12 years ago in reply to yuxi

TI__Guru 59700 points

The memory map changes are wrong. Use the default memory map that is part of DVR RDK for 2G memory configuration

0 yuxi over 12 years ago in reply to Badri Narayanan

Intellectual 650 points

But if I want to increase the tiler memory, and decrease the SR1, SR2, SR3 memory, How could I modify the default 2G configuration?

0 Badri Narayanan over 12 years ago in reply to yuxi

TI__Guru 59700 points

You cannot increase Tiler memory beyond 256MB. This is h/w limitation

0 yuxi over 12 years ago in reply to Badri Narayanan

Intellectual 650 points

If I want to modify the HDVPSS_SHARED_ADDR,NOTIFY_SHARED_ADDR, REMOTE_DEBUG_ADDR, How would I modify other configurations in the code and the bootargs?

Thanks.

0 Badri Narayanan over 12 years ago in reply to yuxi

TI__Guru 59700 points

There is a document that is part of DVR RDK release explaining how to change memory map.

0 yuxi over 12 years ago in reply to Badri Narayanan

Intellectual 650 points

Thanks for your help.

I have read the specified part of RDK release, and have known the errors of my configuration of the memory . The reason is some addrss that M3 can not access.

So I need to modify the linux address, and maintain the M3 access address. but the uImage includes the Load Address and Entry Point. I want to make a new uImage, whose Load Address and Entry Point is 0xC0008000 (or 0xD0008000). How could I modify the lsp package?

0 Badri Narayanan over 12 years ago in reply to yuxi

TI__Guru 59700 points

Pls refer Refer http://processors.wiki.ti.com/index.php/DM816x_AM389x_PSP_User_Guide#Auto_detection_of_Kernel_Load_Address_and_Run_Time_RAM_Base_Determination

0 yuxi over 12 years ago in reply to yuxi

Intellectual 650 points

In DM8168 4 decode_display, I use 2 swms for HD display, and the other 2 swms merged to the ipcFramesOut (M3VPSS) -> ipcFramesIn (A8) link connection.

   for (channelNum = 0; channelNum < 4; channelNum++)
   {
    swMsPrm[channelNum].numSwMsInst      = 1;
    swMsPrm[channelNum].inQueParams.prevLinkId   = dupId;
    swMsPrm[channelNum].inQueParams.prevLinkQueId = channelNum;
    swMsPrm[channelNum].swMsInstId[0] = SYSTEM_SW_MS_SC_INST_VIP1_SC + channelNum;

    if(channelNum < 2)
    {
      swMsPrm[channelNum].outQueParams.nextLink = displayId[channelNum];
    }
    else
    {
      swMsPrm[channelNum].outQueParams.nextLink = mergeId;
    }

    swMsPrm[channelNum].lineSkipMode    = FALSE;
    swMsPrm[channelNum].enableLayoutGridDraw = FALSE;
    swMsPrm[channelNum].layoutPrm.outputFPS = DEFAULT_FRAME_RATE;
    swMsPrm[channelNum].maxInputQueLen    = SYSTEM_SW_MS_DEFAULT_INPUT_QUE_LEN;
    swMsPrm[channelNum].maxOutRes     = displayRes[channelNum];
    swMsPrm[channelNum].numOutBuf     = 0;
    swMsLayout1x1Params(&layout_id[0], &swMsPrm[channelNum]);
    //mulich_vdec_vdis_set_avsync_prm(&avsyncCfg[channelNum],channelNum,channelNum);
   }

   for (channelNum = 0; channelNum < DISPALY_CHANNEL; channelNum++)
   {
    displayPrm[channelNum].numInputQueues     = 1;
    displayPrm[channelNum].activeQueue   = 0;
    displayPrm[channelNum].inQueParams[0].prevLinkId = swMsId[channelNum];
    displayPrm[channelNum].inQueParams[0].prevLinkQueId = 0;
    displayPrm[channelNum].displayRes   = displayRes[channelNum];
    displayPrm[channelNum].forceFieldSeparatedInputMode = FALSE;
    //displayPrm[channelNum].maxDriverQueLength = 3;
    //displayPrm[channelNum].queueInISRFlag = TRUE;
   }

   mergePrm.numInQue                      = 2;
   mergePrm.inQueParams[0].prevLinkId     = swMsId[2];
   mergePrm.inQueParams[0].prevLinkQueId = 0;
   mergePrm.inQueParams[1].prevLinkId     = swMsId[3];
   mergePrm.inQueParams[1].prevLinkQueId = 0;
   mergePrm.outQueParams.nextLink         = ipcFramesOutVpssToHost;
   mergePrm.notifyNextLink                = TRUE;

   ipcFramesOutVpssToHostPrm.baseCreateParams.inQueParams.prevLinkId = mergeId;
   ipcFramesOutVpssToHostPrm.baseCreateParams.noNotifyMode = FALSE;
   ipcFramesOutVpssToHostPrm.baseCreateParams.notifyNextLink = TRUE;
   ipcFramesOutVpssToHostPrm.baseCreateParams.notifyPrevLink = FALSE;
   ipcFramesOutVpssToHostPrm.baseCreateParams.inQueParams.prevLinkQueId = 0;
   ipcFramesOutVpssToHostPrm.baseCreateParams.outQueParams[0].nextLink = ipcFramesInA8Id;
   ipcFramesOutVpssToHostPrm.baseCreateParams.inputFrameRate = DEFAULT_FRAME_RATE;
   ipcFramesOutVpssToHostPrm.baseCreateParams.outputFrameRate = DEFAULT_FRAME_RATE;
   ipcFramesOutVpssToHostPrm.baseCreateParams.notifyProcessLink = FALSE;

If I write the every output frame in real-time, It comes segement error. But if I write the frames in every 1000 frames interval or do not write the frames, It runs OK, and comes some warnings:

[m3vpss ] 4951:ERR::linkID:20000037::channelID:-1::errorCode:-3::FileName:links_m3vpss/avsync/avsync_m3vpss.c::linuNum:1236::errorCondition:((avsync_map_linkid2displayid(pObj,cp->syncLinkID) != AVSYNC_INVALID_DISPLAY_ID) || (cp->displayID != AVSYNC_INVALID_DISPLAY_ID))
[m3vpss ] AVSYNC:WARNING!!!.AVSYNC config invalid for linkID[20000034]:chId[0] Will Default to AVSYNC disabled.

Moreover, if I add the function mulich_vdec_vdis_set_avsync_prm(&avsyncCfg[channelNum],channelNum,channelNum) for the program, it also comes segement error.

there may be some errors in the avsync configuration for decoding for two HD display and the other two output YUV to A8. How could I modify the avsync configuration based on the the function mulich_vdec_vdis_set_avsync_prm?

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DM8168 Decoding External Display