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TMS320C6727 McASP initialization problem

Alexander Lange2
Prodigy 20 points

Hello,

we are currently facing a problem with the initialization of the McASP0 of a C6727. We want to transmit data using the CPU to writte into the XBUF0 whenever the correponding flag indicates a ready signal. Initialization for the format seems to be fine, as we have clocks and the frame signal also fits our configuration. The code is attached, here is only the current part where we initialize. It's also interesting to see that it will never transmitt when free runnning, and only once if we step through the init manually. It never transmits when we are in the while(1) loop in the main. This makes us suspect that there is something wrong with the clocks, but we tried several different settings and combinations for the clock dividers, without success. The attached pictures show the one transmission we get when stepping manualy, which looks just fine, but then the second picture shows the signals at normal operation. Green is XCLK0, blue the frame sync, and yellow the AXR0. The transmission sends 0x5F0AF50 as expected, but only in frame 0, nothing in frame 1. We tried the burst mode, which works fine, and more frames, but they don't transmitt as well.

void initMcASP0(void)
{
	McASP0[GBLCTL]=0x0;
	McASP0[PWRDEMU]=0x1;
	McASP0[XMASK]=0xFFFFFFFF; 	// No replacing of Bits
	McASP0[XFMT]= 0x80F8; 		// 00 delay, 1 MSB First, 0 Pad, 0 value, 0xF SlotSize 32, 1 Peripheral Bus, 000 no rotation
	McASP0[AFSXCTL]= 0x112; 	// 0x2 Slots, 00 reserved, 1 Word, 00 reserved, 1 internal, 0 rising edge
	McASP0[ACLKXCTL]= 0x3F;		// 0 rising edge, 0 Sync, 1 internal, 0x1F Divide by 32
	McASP0[AHCLKXCTL]= 0x8000;	// 1 internal, 0 rising edge, 00 reserved, 0 divide AUXCLK by 1
	McASP0[XTDM]= 0x1; 			// slots 0 and 1 active
	McASP0[XINTCTL]= 0x0; 		// no interrupts
	McASP0[XCLKCHK]= 0xFF0005; 	// 0xFF maximum, 0x00 minimum, 0 autoswitch disabled, 000 reserved, 0x5 prescaler 32
	McASP0[SRCTL0]= 0x1;		// 0 RRDY, 0 XRDY, 0 3-State, 01 Transmitter
	McASP0[PFUNC]= 0x0; 		// McASP occupies all Pins
	McASP0[PDIR]= McASP0[PDIR] | 0x1E00000F; 	// 1E00000F Frame Sync, HCLK, CLK, AMUTE AXR0-7 as Outputs for McASP0
	McASP0[DITCTL]= 0x0; 		// DIT mode disabled
	McASP0[DLBCTL]= 0x0; 		// Loopback disabled
	McASP0[AMUTE]= 0x0; 		// AMUTE disabled
	McASP0[GBLCTL]= McASP0[GBLCTL] | 0x202; // Enable RHCLK and XHCLK
	while(!(McASP0[GBLCTL] & 0x202));
	McASP0[GBLCTL]= McASP0[GBLCTL] | 0x101; // Enable RCLK and XCLK
	while(!(McASP0[GBLCTL] & 0x101));
	McASP0[XSTAT]= 0xFFFF;		// Clear all status registers
	McASP0[RSTAT]= 0xFFFF;
	McASP0[GBLCTL]= McASP0[GBLCTL] | 0x404; // Enable Serializers
	while(!(McASP0[GBLCTL] & 0x404));
	McASP0[XBUF0]= 0x5F0AF50A;		// Sending AAAA in the first comand
	McASP0[GBLCTL]= McASP0[GBLCTL] | 0x808; // Enable State Machines
	while(!(McASP0[GBLCTL] & 0x808));
	McASP0[GBLCTL]= McASP0[GBLCTL] | 0x1010; // Enable Frame Syncs
	while(!(McASP0[GBLCTL] & 0x1010));
	while((McASP0[SRCTL0] & 0x00000010) != 0x00000010);
}

int main(void) {
	initMcASP0();
	while(1)
	{
		while((McASP0[SRCTL0] & 0x00000010) != 0x00000010);
		McASP0[XBUF0]=0xBEEF;
	}
	return 0;
}

 

The transmission when steping manually:

 

The "normal" operation (using 2 frames, 32 Bit, Sync duration 1 word):

 

Does somebody know what do we do wrong in the initialization, that it does not transmitt continuously when we feed the buffer with the CPU? We would expect something similar to the burst mode, which works fine. Thank you very much for your help!

Fullscreen 0257.McASP code.txt Download 
/*
 * main.c
 */

extern far int McASP0[0x2BF];
extern far int McASP1[0x2BF];
extern far int McASP2[0x2BF];

#define GBLCTL 		(0x44/4)

#define PWRDEMU 	(0x04/4)
#define RMASK		(0x64/4)
#define RFMT		(0x68/4)
#define AFSRCTL		(0x6C/4)
#define ACLKRCTL	(0x70/4)
#define AHCLKRCTL	(0x74/4)
#define RTDM		(0x78/4)
#define RINTCTL		(0x7C/4)
#define RCLKCHK		(0x88/4)

#define XMASK		(0xA4/4)
#define XFMT		(0xA8/4)
#define AFSXCTL		(0xAC/4)
#define ACLKXCTL	(0xB0/4)
#define AHCLKXCTL	(0xB4/4)
#define XTDM		(0xB8/4)
#define XINTCTL		(0xBC/4)
#define XCLKCHK		(0xC8/4)

#define SRCTL0		(0x180/4)
#define SRCTL1		(0x184/4)
#define SRCTL2		(0x188/4)
#define SRCTL3		(0x18C/4)
#define SRCTL4		(0x190/4)
#define SRCTL5		(0x194/4)
#define SRCTL6		(0x198/4)
#define SRCTL7		(0x19C/4)
#define SRCTL8		(0x1A0/4)
#define SRCTL9		(0x1A4/4)
#define SRCTL10		(0x1A8/4)
#define SRCTL11		(0x1AC/4)
#define SRCTL12		(0x1B0/4)
#define SRCTL13		(0x1B4/4)
#define SRCTL14		(0x1B8/4)
#define SRCTL15		(0x1BC/4)

#define PFUNC		(0x10/4)
#define PDIR		(0x14/4)
#define DITCTL		(0x50/4)
#define DLBCTL		(0x4C/4)
#define AMUTE		(0x48/4)

#define XSTAT		(0xC0/4)
#define RSTAT		(0x80/4)

#define XBUF0 		(0x200/4)
#define XBUF1 		(0x204/4)
#define XBUF2 		(0x208/4)
#define XBUF3 		(0x20C/4)
#define XBUF4 		(0x210/4)
#define XBUF5 		(0x214/4)
#define XBUF6 		(0x218/4)
#define XBUF7 		(0x21C/4)
#define XBUF8 		(0x220/4)
#define XBUF9 		(0x224/4)
#define XBUF10 		(0x228/4)
#define XBUF11		(0x22C/4)
#define XBUF12		(0x230/4)
#define XBUF13		(0x234/4)
#define XBUF14		(0x238/4)
#define XBUF15		(0x23C/4)

#define RBUF0 		(0x280/4)
#define RBUF1 		(0x284/4)
#define RBUF2 		(0x288/4)
#define RBUF3 		(0x28C/4)
#define RBUF4 		(0x290/4)
#define RBUF5 		(0x294/4)
#define RBUF6 		(0x298/4)
#define RBUF7 		(0x29C/4)
#define RBUF8 		(0x2A0/4)
#define RBUF9 		(0x2A4/4)
#define RBUF10 		(0x2A8/4)
#define RBUF11		(0x2AC/4)
#define RBUF12		(0x2B0/4)
#define RBUF13		(0x2B4/4)
#define RBUF14		(0x2B8/4)
#define RBUF15		(0x2BC/4)


void initMcASP0(void)
{
	McASP0[GBLCTL]=0x0;
	McASP0[PWRDEMU]=0x1;
	McASP0[XMASK]=0xFFFFFFFF; 	// No replacing of Bits
	McASP0[XFMT]= 0x80F8; 		// 00 delay, 1 MSB First, 0 Pad, 0 value, 0xF SlotSize 32, 1 Peripheral Bus, 000 no rotation
	McASP0[AFSXCTL]= 0x112; 	// 0x2 Slots, 00 reserved, 1 Word, 00 reserved, 1 internal, 0 rising edge
	McASP0[ACLKXCTL]= 0x3F;		// 0 rising edge, 0 Sync, 1 internal, 0x1F Divide by 32
	McASP0[AHCLKXCTL]= 0x8000;	// 1 internal, 0 rising edge, 00 reserved, 0 divide AUXCLK by 1
	McASP0[XTDM]= 0x1; 			// slots 0 and 1 active
	McASP0[XINTCTL]= 0x0; 		// no interrupts
	McASP0[XCLKCHK]= 0xFF0005; 	// 0xFF maximum, 0x00 minimum, 0 autoswitch disabled, 000 reserved, 0x5 prescaler 32
	McASP0[SRCTL0]= 0x1;		// 0 RRDY, 0 XRDY, 0 3-State, 01 Transmitter
	McASP0[PFUNC]= 0x0; 		// McASP occupies all Pins
	McASP0[PDIR]= McASP0[PDIR] | 0x1E00000F; 	// 1E00000F Frame Sync, HCLK, CLK, AMUTE AXR0-7 as Outputs for McASP0
	McASP0[DITCTL]= 0x0; 		// DIT mode disabled
	McASP0[DLBCTL]= 0x0; 		// Loopback disabled
	McASP0[AMUTE]= 0x0; 		// AMUTE disabled
	McASP0[GBLCTL]= McASP0[GBLCTL] | 0x202; // Enable RHCLK and XHCLK
	while(!(McASP0[GBLCTL] & 0x202));
	McASP0[GBLCTL]= McASP0[GBLCTL] | 0x101; // Enable RCLK and XCLK
	while(!(McASP0[GBLCTL] & 0x101));
	McASP0[XSTAT]= 0xFFFF;		// Clear all status registers
	McASP0[RSTAT]= 0xFFFF;
	McASP0[GBLCTL]= McASP0[GBLCTL] | 0x404; // Enable Serializers
	while(!(McASP0[GBLCTL] & 0x404));
	McASP0[XBUF0]= 0x5F0AF50A;		// Sending AAAA in the first comand
	McASP0[GBLCTL]= McASP0[GBLCTL] | 0x808; // Enable State Machines
	while(!(McASP0[GBLCTL] & 0x808));
	McASP0[GBLCTL]= McASP0[GBLCTL] | 0x1010; // Enable Frame Syncs
	while(!(McASP0[GBLCTL] & 0x1010));
	while((McASP0[SRCTL0] & 0x00000010) != 0x00000010);
}

int main(void) {
	initMcASP0();
	while(1)
	{
		while((McASP0[SRCTL0] & 0x00000010) != 0x00000010);
		McASP0[XBUF0]=0xBEEF;
	}
	return 0;
}

  • 0
    TI__Mastermind 35645 points

    Hi Alexander,

    Thanks for your post.

    Please ensure and validate the steps in the McASP setup and initialization Section 3.1.1 in the C672x McASP reference guide as refered below:

    http://www.ti.com/lit/ug/spru878b/spru878b.pdf

    Kindly note that, if external clocks are used, clocks should be running before following the initialization steps followed in the above reference guide. Please take care on the same.

    In your code, who is servicing the McASP's XRBUF? DMA or CPU? Also, please check the caution mentioned in the above reference guide while writing to the XRBUF through CCS. It seems, there is a restriction on the emulation read from the XRBUF locations.

    Thanks & regards,
    Sivaraj K

    ------------------------------------------------------------------------------------------------------- 
    Please click the Verify Answer button on this post if it answers your question.
    --------------------------------------------------------------------------------------------------------

     

     

  • 0 in reply to Sivaraj Kuppuraj
    Prodigy 20 points

    Hi Sivaraj,

    we got a transmission to work using the following code:

     

    void initMcASP0(void)
{
	McASP0[GBLCTL]=0x0;
	McASP0[PWRDEMU]=0x1;
	McASP0[XMASK]=0xFFFFFFFF; 	// No replacing of Bits
	McASP0[XFMT]= 0x80F8; 		// 00 delay, 1 MSB First, 0 Pad, 0 value, 0xF SlotSize 32, 1 Peripheral Bus, 000 no rotation
	McASP0[AFSXCTL]= 0x112; 	// 0x2 Slots, 00 reserved, 1 Word, 00 reserved, 1 internal, 0 rising edge
	McASP0[ACLKXCTL]= 0x3F;		// 0 rising edge, 0 Sync, 1 internal, 0x1F Divide by 32
	McASP0[AHCLKXCTL]= 0x8000;	// 1 internal, 0 rising edge, 00 reserved, 0 divide AUXCLK by 1
	McASP0[XTDM]= 0x3; 			// slots 0 and 1 active
	McASP0[XINTCTL]= 0x0; 		// no interrupts
	McASP0[XCLKCHK]= 0xFF0005; 	// 0xFF maximum, 0x00 minimum, 0 autoswitch disabled, 000 reserved, 0x5 prescaler 32
	McASP0[SRCTL0]= 0x1;		// 0 RRDY, 0 XRDY, 0 3-State, 01 Transmitter
	McASP0[PFUNC]= 0x0; 		// McASP occupies all Pins
	McASP0[PDIR]= McASP0[PDIR] | 0x1E00000F; 	// 1E00000F Frame Sync, HCLK, CLK, AMUTE AXR0-7 as Outputs for McASP0
	McASP0[DITCTL]= 0x0; 		// DIT mode disabled
	McASP0[DLBCTL]= 0x0; 		// Loopback disabled
	McASP0[AMUTE]= 0x0; 		// AMUTE disabled
	McASP0[GBLCTL]= McASP0[GBLCTL] | 0x202; // Enable RHCLK and XHCLK
	while(!(McASP0[GBLCTL] & 0x202));
	delayCycles(1000);
	McASP0[GBLCTL]= McASP0[GBLCTL] | 0x101; // Enable RCLK and XCLK
	while(!(McASP0[GBLCTL] & 0x101));
	delayCycles(1000);
	McASP0[XSTAT]= 0xFFFF;		// Clear all status registers
	McASP0[RSTAT]= 0xFFFF;
	McASP0[GBLCTL]= McASP0[GBLCTL] | 0x404; // Enable Serializers
	while(!(McASP0[GBLCTL] & 0x404));
	delayCycles(1000);
	McASP0[XBUF0]= 0x5F0AF50A;		// Sending AAAA in the first comand
	McASP0[GBLCTL]= McASP0[GBLCTL] | 0x808; // Enable State Machines
	while(!(McASP0[GBLCTL] & 0x808));
	delayCycles(1000);
	McASP0[GBLCTL]= McASP0[GBLCTL] | 0x1010; // Enable Frame Syncs
	while(!(McASP0[GBLCTL] & 0x1010));
}

    It is basicaly the same as the first one, and I had already followed the instruction you mentioned. The only difference now is, that we delay 1000 cycles after every change in GBLCTL. This seems to work, and we asume that the CPU writes the Register so fast that the McASP can't keep up with the changes happening so qickly. We have not tried to use less delays or less delayed cycles for every delay, as initialization speed is not important for us, and the necessary delay will probably also strongly depend on the ratio of CPU speed / McASP speed.

    We are generating all clocks internaly, and the cpu is still polling the SRCTL0 register for feeding the buffer.

    Is it mentioned somewhere in the McASP reference, that we need delays, and how long these need to be? It only says that we need to read back the GBLCTL register, which we already did in our problematic code I posted earlier.

    Thank you for your help,

    Alexander