Gel file : DDR3 memory test ... Failed

Brandy Jabkiewicz

Hi,

I am a software engineer working on our custom board. Yesterday, my setup was working - I was able to communicate to two C6678 via the a Black Hawk emulator and execute code. I did not make any changes to my gel file and now it seems it is not working. I cannot try another board because we only have one :(

Here are my steps:

Connect to target

Perform system reset

Load gel file

Run global_default_setup

(let it finish - it seems to run the function call 7 or 8 times instead of once like when it is working)

Load .out

(it never gets to main. the code is corrupted.)

My questions are:

Where is the DDR memory test coming from? I searched the gel file and there is no code with those output words.

Could I have written some code that ruined the hardware? I did not make many changes between yesterday and today - I just moved some variables around (in MSMCSRAM) and tried to run it again.

What are some hints that I could look at to see what this problem is?

I've power cycled, tried different emulators and everytime is the same output by the gel file. My executable is in DDR3 so I can see why it wouldn't work if it can't load the executable. But I don't get why.

Here is the gel file and the console window:

2642.evmc6678l.gel

Fullscreen 8015.console.txt Download

C66xx_0: GEL Output: Setup_Memory_Map...
C66xx_0: GEL Output: Setup_Memory_Map... Done.
C66xx_1: GEL Output: Setup_Memory_Map...
C66xx_1: GEL Output: Setup_Memory_Map... Done.
C66xx_2: GEL Output: Setup_Memory_Map...
C66xx_2: GEL Output: Setup_Memory_Map... Done.
C66xx_3: GEL Output: Setup_Memory_Map...
C66xx_3: GEL Output: Setup_Memory_Map... Done.
C66xx_4: GEL Output: Setup_Memory_Map...
C66xx_4: GEL Output: Setup_Memory_Map... Done.
C66xx_5: GEL Output: Setup_Memory_Map...
C66xx_5: GEL Output: Setup_Memory_Map... Done.
C66xx_6: GEL Output: Setup_Memory_Map...
C66xx_6: GEL Output: Setup_Memory_Map... Done.
C66xx_7: GEL Output: Setup_Memory_Map...
C66xx_7: GEL Output: Setup_Memory_Map... Done.
C66xx_8: GEL Output: Setup_Memory_Map...
C66xx_8: GEL Output: Setup_Memory_Map... Done.
C66xx_9: GEL Output: Setup_Memory_Map...
C66xx_9: GEL Output: Setup_Memory_Map... Done.
C66xx_10: GEL Output: Setup_Memory_Map...
C66xx_10: GEL Output: Setup_Memory_Map... Done.
C66xx_11: GEL Output: Setup_Memory_Map...
C66xx_11: GEL Output: Setup_Memory_Map... Done.
C66xx_12: GEL Output: Setup_Memory_Map...
C66xx_12: GEL Output: Setup_Memory_Map... Done.
C66xx_13: GEL Output: Setup_Memory_Map...
C66xx_13: GEL Output: Setup_Memory_Map... Done.
C66xx_14: GEL Output: Setup_Memory_Map...
C66xx_14: GEL Output: Setup_Memory_Map... Done.
C66xx_15: GEL Output: Setup_Memory_Map...
C66xx_15: GEL Output: Setup_Memory_Map... Done.
C66xx_0: GEL Output: 
Connecting Target...
C66xx_0: GEL Output: DSP core #0
C66xx_0: GEL Output: No initialization performed since bootmode = 0x00000005 
C66xx_0: GEL Output: You can manually initialize with GlobalDefaultSetup
C66xx_1: GEL Output: 
Connecting Target...
C66xx_1: GEL Output: DSP core #1
C66xx_1: GEL Output: No initialization performed since bootmode = 0x00000005 
C66xx_1: GEL Output: You can manually initialize with GlobalDefaultSetup
C66xx_2: GEL Output: 
Connecting Target...
C66xx_2: GEL Output: DSP core #2
C66xx_2: GEL Output: No initialization performed since bootmode = 0x00000005 
C66xx_2: GEL Output: You can manually initialize with GlobalDefaultSetup
C66xx_3: GEL Output: 
Connecting Target...
C66xx_3: GEL Output: DSP core #3
C66xx_3: GEL Output: No initialization performed since bootmode = 0x00000005 
C66xx_3: GEL Output: You can manually initialize with GlobalDefaultSetup
C66xx_4: GEL Output: 
Connecting Target...
C66xx_4: GEL Output: DSP core #4
C66xx_4: GEL Output: No initialization performed since bootmode = 0x00000005 
C66xx_4: GEL Output: You can manually initialize with GlobalDefaultSetup
C66xx_5: GEL Output: 
Connecting Target...
C66xx_5: GEL Output: DSP core #5
C66xx_5: GEL Output: No initialization performed since bootmode = 0x00000005 
C66xx_5: GEL Output: You can manually initialize with GlobalDefaultSetup
C66xx_0: GEL Output: C6678L GEL file Ver is 2.005 
C66xx_0: GEL Output: Global Default Setup...
C66xx_0: GEL Output: Setup Cache... 
C66xx_0: GEL Output: L1P = 32K   
C66xx_0: GEL Output: L1D = 32K   
C66xx_0: GEL Output: L2 = ALL SRAM   
C66xx_0: GEL Output: Setup Cache... Done.
C66xx_0: GEL Output: Main PLL (PLL1) Setup ... 
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller... 
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output:            SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output:            SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... 
C66xx_0: GEL Output: Security Accelerator disabled!
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: PA PLL (PLL3) Setup ... 
C66xx_0: GEL Output: PA PLL Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... 
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done 
C66xx_0: GEL Output: 
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: Main PLL (PLL1) Setup ... 
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller... 
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output:            SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output:            SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: PA PLL (PLL3) Setup ... 
C66xx_0: GEL Output: PA PLL Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... 
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done 
C66xx_0: GEL Output: 
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: Main PLL (PLL1) Setup ... 
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller... 
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output:            SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output:            SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: PA PLL (PLL3) Setup ... 
C66xx_0: GEL Output: PA PLL Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... 
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done 
C66xx_0: GEL Output: 
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: Main PLL (PLL1) Setup ... 
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller... 
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output:            SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output:            SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: PA PLL (PLL3) Setup ... 
C66xx_0: GEL Output: PA PLL Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... 
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done 
C66xx_0: GEL Output: 
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: Main PLL (PLL1) Setup ... 
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller... 
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output:            SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output:            SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: PA PLL (PLL3) Setup ... 
C66xx_0: GEL Output: PA PLL Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... 
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done 
C66xx_0: GEL Output: 
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: Main PLL (PLL1) Setup ... 
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller... 
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output:            SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output:            SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: PA PLL (PLL3) Setup ... 
C66xx_0: GEL Output: PA PLL Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... 
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done 
C66xx_0: GEL Output: 
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: Main PLL (PLL1) Setup ... 
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller... 
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output:            SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output:            SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: PA PLL (PLL3) Setup ... 
C66xx_0: GEL Output: PA PLL Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... 
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done 
C66xx_0: GEL Output: 
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: Main PLL (PLL1) Setup ... 
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller... 
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output:            SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output:            SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: PA PLL (PLL3) Setup ... 
C66xx_0: GEL Output: PA PLL Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... 
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done 
C66xx_0: GEL Output: 
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: Main PLL (PLL1) Setup ... 
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller... 
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output:            SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output:            SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: PA PLL (PLL3) Setup ... 
C66xx_0: GEL Output: PA PLL Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... 
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done 
C66xx_0: GEL Output: 
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: Main PLL (PLL1) Setup ... 
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller... 
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output:            SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output:            SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: PA PLL (PLL3) Setup ... 
C66xx_0: GEL Output: PA PLL Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... 
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done 
C66xx_0: GEL Output: 
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: PLL and DDR Initialization failed ...
C66xx_0: GEL Output: configSGMIISerdes Setup... Begin
C66xx_0: GEL Output: 
SGMII SERDES has been configured.
C66xx_0: GEL Output: Enabling EDC ...
C66xx_0: GEL Output: L1P error detection logic is enabled.
C66xx_0: GEL Output: L2 error detection/correction logic is enabled.
C66xx_0: GEL Output: MSMC error detection/correction logic is enabled.
C66xx_0: GEL Output: Enabling EDC ...Done 
C66xx_0: GEL Output: Configuring CPSW ...
C66xx_0: GEL Output: Configuring CPSW ...Done 
C66xx_0: GEL Output: Global Default Setup... Done.
C66xx_0: GEL Output: Invalidate All Cache...
C66xx_0: GEL Output: Invalidate All Cache... Done.
C66xx_0: GEL Output: GEL Reset...
C66xx_0: GEL Output: GEL Reset... Done.
C66xx_0: GEL Output: Disable all EDMA3 interrupts and events.
C66xx_1: GEL Output: Invalidate All Cache...
C66xx_1: GEL Output: Invalidate All Cache... Done.
C66xx_1: GEL Output: GEL Reset...
C66xx_1: GEL Output: GEL Reset... Done.
C66xx_2: GEL Output: Invalidate All Cache...
C66xx_2: GEL Output: Invalidate All Cache... Done.
C66xx_2: GEL Output: GEL Reset...
C66xx_2: GEL Output: GEL Reset... Done.
C66xx_3: GEL Output: Invalidate All Cache...
C66xx_3: GEL Output: Invalidate All Cache... Done.
C66xx_3: GEL Output: GEL Reset...
C66xx_3: GEL Output: GEL Reset... Done.
C66xx_4: GEL Output: Invalidate All Cache...
C66xx_4: GEL Output: Invalidate All Cache... Done.
C66xx_4: GEL Output: GEL Reset...
C66xx_4: GEL Output: GEL Reset... Done.
C66xx_5: GEL Output: Invalidate All Cache...
C66xx_5: GEL Output: Invalidate All Cache... Done.
C66xx_5: GEL Output: GEL Reset...
C66xx_5: GEL Output: GEL Reset... Done.

Thanks for the advice.

Brandy

over 12 years ago

0 Brandy Jabkiewicz over 12 years ago

Mastermind 6325 points

I should mention, the code will still execute on an EVM as well, so I know the .out file is ok.

Thanks again,

0 Mahendra varman over 12 years ago in reply to Brandy Jabkiewicz

Intellectual 500 points

In my custom board I faced same situation

Found out that the EVM and my custom board has different DDR part.

So I adjusted Timing values of the DDR that suits my custom board's DDR memory in the gel file

Loaded the modified gel file and the problem gone..

Hope it may help u

Thanks

Mahendra

0 Brandy Jabkiewicz over 12 years ago in reply to Mahendra varman

Mastermind 6325 points

Hi Mahendra,

I will double check but I think we used the same part. Also, it was working on Tuesday and Wednesday but would not work on Thursday, as though something failed over night. But I am not sure what to check.

Do you know where the code is for the DDR test that is failing so I can look at it? Maybe there is a hint. I remember with the Davinci, it was possible for the DDR test to fail but everything was still ok. There was a case where it was expecting memory to be cleared to a certain value and failed if it wasn't - but the part was still ok.

Thanks,
Brandy

0 GregorS over 12 years ago in reply to Brandy Jabkiewicz

Intellectual 500 points

hi Brandy,

for my EMV (c6657) the DDR3 test/init things are in: pdk_C6657_1_1_2_6\packages\ti\platform\evmc6657l\platform_test\src and pdk_C6657_1_1_2_6\packages\ti\platform\evmc6657l\platform_lib\src.

Is this the code you are looking for?

Regards, Gregor

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Gel file : DDR3 memory test ... Failed