Receiving unidentified interrupts from UART on C6747

Yoav Gold

Hi,
I'm writing a UART interrupt driver using the CSL.
Working with the Rx interrupts causes no problem...I'm getting the Timeout interrupt and the Threshold interrupt with no problem.
Because all UART interrupts (Rx, Tx, Modem Status) are connected with the same event ( #69 ) and there for, they are connected to the same interrupt,
I configured the IER as so :

BSW_t_Uart2Regs->IER = CSL_FMKT(UART_IER_EDSSI, DISABLE )
        |   CSL_FMKT(UART_IER_ELSI , DISABLE )
        |   CSL_FMKT(UART_IER_ETBEI, ENABLE )
        |   CSL_FMKT(UART_IER_ERBI , ENABLE );

I decided that after receiving the interrupt, Ill look in the IIR and check what kind of interrupt is it Like so :
e_IrqType = CSL_FEXT(BSW_t_Uart2Regs->IIR, UART_IIR_INTID).
Later I'm using a swith-case and do other operations according to the event at hand.

The problem is, that after I enable the TxFifoEmpty event ( CSL_FMKT(UART_IER_ETBEI, ENABLE ) ), once in a while
I'm starting to get interrupts without an ID on the IIR
I mean that CSL_FEXT(BSW_t_Uart2Regs->IIR, UART_IIR_INTID) results with '0x0000'.
This problem seems to cause me to "MISS" Rx interrupts...(for example, i'm sending 100 bytes to the serial port
via a PC application, and once every couple of Transmits, 1 of the bytes wownt arrive to the DSP).
Any Ideas?

Thank,
Yoav

Additional information :
I made sure that I dont get nested interrupts , this doesnt happen when Fifo TX interrupt is disabled,
this doesnt happen if I'm not trying to send data via the RS232.
I'm using CC3.3, Bios 5.41.01.09, C.G.T 6.1.12

over 15 years ago

0 Mukul Bhatnagar over 15 years ago

TI__Guru* 84325 points

Hi Yoav

We recently found that the IIR register is impacted by emulation reads ( contrary to what is mentioned the UART user guide:SPRUFM6a section 2.11 para 2), so if you had a memory window open in CCS in the UART MMR space, a refresh/breakpoint could cause an emulation read , clearing the IIR register.

Additionally in the same user guide, Table 11 (Pg 26) mentions that for the Interrupt type: Transmit Holding Register Empty , Event that clears the interrupt is "a character written to the THR" --> This description is incomplete, as additionally this interrupt condition can also get cleared on a read issued to the IIR register.We are in process of updating the document to reflect these changes.

Could this be the source of your issue? If your ISR is reading IIR it might be clearing a ETBEI condition when you were servicing a receive interrupt?

If this is indeed the source of your issue, I apologize for the inconvinience caused by the incomplete documentation.

Hope this helps

Regards

Mukul

0 Yoav Gold over 15 years ago in reply to Mukul Bhatnagar

Prodigy 250 points

Hi Mukul,

Well, This can explain some of the unidentified interrupts but it does not explain the missing bytes.
I decided that I will try and read bytes even if I got these "Empty" interrupts.
I held 2 tests :

1.In case I get this "empty" interrupt, I configured my routine to go to the RBR
and read data from there as long as there is still data in the fifo :
while(CSL_FEXT(BSW_t_Uart2Regs->LSR, UART_LSR_DR) == CSL_UART_LSR_DR_READY)
{
pu8_RecBuffer[u16_WriteIndex] = CSL_FEXT(BSW_t_Uart2Regs->RBR, UART_RBR_DATA);
u16_WriteIndex = ((u16_WriteIndex + 1) % u32_BufferSize);
}
This resulted in the same way, I keep on "loosing" bytes once in a while
2. In case I get this "empty" interrupt, I configured my routine to go and read from the RBR regardless of the
FIFO state.
This resulted with getting '0' instead of the bytes I missed.

It looks now like the problem isn't interrupt related at all but it is related to the actual process of the Transmit and Receive.
I took some more tests :
I disabled the Tx interrupt and moved it to be the highest priority Task, Checking the Fifo and Shift register are empty
and sending X bytes (X<16) each time before going to sleep for 1 Milisec.
I left the Rx IRQ and ISR as they were.

Now, I started the operation (1 Byte as a Rx Threshold, EDSSI ELSI and ERBI Enabled).
I don't get these empty interrupts any more, but I keep on loosing bytes.
i.e : I'm sending 200 bytes via the serial port, I'm receiving 200 interrupts, 198 are Data ready interrupts, 2 are empty interrupts.
In this situation, I managed to read 198 bytes out of the Fifo.

Can you see how these things are connected?

0 Mukul Bhatnagar over 15 years ago in reply to Yoav Gold

TI__Guru* 84325 points

Hi Yoav

So this is w.r.t to your other related post

I think I would need to ask a few more questions to dwell deeper into this (sorry if they are too many).

What is the baud rate for your UART setup?Does the problem exist if baud rate was lowered?

What is your RX/TX setup (is it a digital loopback test)?If it is DLB, can this test be done with 2 UARTs instead?

What is the pattern of failure/lost bytes i.e. e.g. do you loose bytes in a random order?

Does changing the rx threshold alleviate the issue?

(Lower Priority Q)

Any reason why you are not using EDMA to service the UART transfers (incurring an interrupt for every byte would eventually cause issues in your complete system IMHO)?

Also, note that you mention enabling EDSSI bit, in the IER register. I know in the past (on previous devices) we have not supported this bit being enabled (always write 0). I see that this is "partially" described in the user guide. I wonder if not enabling EDSSI bit changes the behavior.I will try to find more on this.

Regards

Mukul

0 Yoav Gold over 15 years ago in reply to Mukul Bhatnagar

Prodigy 250 points

Mukul Bhatnagar said:

Hi Yoav

So this is w.r.t to your other related post

I think I would need to ask a few more questions to dwell deeper into this (sorry if they are too many).

What is the baud rate for your UART setup?Does the problem exist if baud rate was lowered?

What is your RX/TX setup (is it a digital loopback test)?If it is DLB, can this test be done with 2 UARTs instead?

What is the pattern of failure/lost bytes i.e. e.g. do you loose bytes in a random order?

Does changing the rx threshold alleviate the issue?

(Lower Priority Q)

Any reason why you are not using EDMA to service the UART transfers (incurring an interrupt for every byte would eventually cause issues in your complete system IMHO)?

Also, note that you mention enabling EDSSI bit, in the IER register. I know in the past (on previous devices) we have not supported this bit being enabled (always write 0). I see that this is "partially" described in the user guide. I wonder if not enabling EDSSI bit changes the behavior.I will try to find more on this.

Regards

Mukul

Well

- I'm working in 115200, I didnt get to check it at a lower baud rate because our system load demands it. I can do this for testing purposes.

- Loopback mode showes no errors, but I think that the parallelity of the system is not fully simulated in this way.
We only get errors when transmitting from an external application.

- As long as I read the bytes only after a RX interrupt, I cannot put my fingure on a failure pattern But in case I go and try to read the data even for these unidentified interrupts, then I get a different value (A value that was sent to me in this specific run), the value I was suppose to get gets lost and after that, all goes back to normal (Until next unidentified interrupt).

- Raising the threshold does elevate the issue.

- We tried working with EDMA (using the GIO based mini driver) and we encountered many instability problems when stressing the system. because we couldnt really see what is going on inside the mini-driver and the israely support team didn't come in usefull we decided to give it up and work with interrupt.

Ask all the questions we need, we really need some help in this issue

Thanks

Yoav

0 Mukul Bhatnagar over 15 years ago in reply to Yoav Gold

TI__Guru* 84325 points

Hi Yoav

Thanks for the additional information.

Can you please also rule out any unknown issues being caused by EDSSI enabled ( I still need to confirm whether it is supported or not). FYI, I think the INTID value of 0x0 is probably likely because of the modem status interrupt (EDSSI)

It would be good to see if disabling this takes care of your "unidentified" interrupts, and then we can just focus on the lost byte issues (assuming it is independent of this setting)

Here is a snapshot from the specification documentation, see last row in the table.

0 Yoav Gold over 15 years ago in reply to Mukul Bhatnagar

Prodigy 250 points

Hi again mukul,

Ill look into the EDSSI thing again, but as I recall it, I just recently enabled it and I got those interrupts from start.
As I see it, the unidenified interrupts are completly connected to the Lost byte...I figure this because If I send X bytes from a terminal
to the DSP I get X-z DR interrupts and z unidenified interrupts.

by any chance can this be something inside the DSP (HW?)

Thanks again

Yoav

0 Mukul Bhatnagar over 15 years ago in reply to Yoav Gold

TI__Guru* 84325 points

Yoav

I am pretty positive that this is not a device issue. The UARTs on these devices are robust and don't have any hardware issues. The baudrate that you are trying to operate at is typical baudrate, so I don't expect this to be an issue (trying to lower the baudrate for test purposes is still a good experiment).

While we typically recommend using EDMA for UARTs (at least in the long run from a system loading and CPU off loading purposes) I don't expect CPU interrupt/polling based transfers to have any issues either (specially if currently you have only UARTs in your system and no other peripheral/CPU loading?)

I am not sure what issues/instability you were facing with the PSP UART drivers, but since you are not making use of the TI drivers, we will continue trying to understand what software/ custom board issues might be impacting your implementation.

Keep us posted on the experiments and please share any other observations that might help peel this more.

Regards

Mukul

0 Yoav Gold over 15 years ago in reply to Mukul Bhatnagar

Prodigy 250 points

Hi Mukul,

I have tested the EDSSI issue and I kept on getting an INTID of value 0x0.
I tried to read the value of the Line Status and the Modem Status after receiving the interrupt but I saw nothing unusual.
I Also tried to disable the ELSI and stayed only with the ERBI but I still got those interrupts.

Ill try to write now more things I didnt write before, Maybe will get a better picture of the situation :
1. Event #69 (UART2) is listed in the tcf file under INT4, using the dispathcer,
   sending an argument and masking all other interrupts.
2. The Testes have been held with UART0 (Event #38) as well.
3. We have held 2 Loopback tests :
     - SW configurated Loopback (using the MCR Register)
     - Hard Loopback (Connecting the Tx and the Rx on the connector).
     Both these tests didnt result in any of the problems above...This makes us wonder if the problem is sync-related?
    (Maybe something with reading from the RBR and writing to the THR at the same time.
4.We tried "protecting" the RBR and the THR by using HWI_disable and HWI_restore...same results
5.I read something in the C6747 errata, something about the ECM :
"The ECM expects all incoming interrupts to be pulse interrupts, however the
[SYSCFG_CHIPSIG_]CHIPINTn interrupts are level interrupts. This mismatch in interrupt
types will cause a single CHIPINTn interrupt event to register multiple times in the ECM."
Can you see if this is related?
6.We tried using/Not using parity, using 1 or 2 stop bits.
7.We changed HW, Connectors, PC, terminal...All with the same results.

I'm gonna try lowering the baudrate, to see if it makes a different.
Do have any idae where else can we try to "cut" the problem in half?
so we will be more sure if the problem is HW/DSP/SW related?

Thanks for your help, All us guys here really appreciate it.

Yoav

0 Mukul Bhatnagar over 15 years ago in reply to Yoav Gold

TI__Guru* 84325 points

Hi Yoav

Thanks for the additional details on this. It is hard for me to comprehend how you would be getting INTID of value 0x0 without EDSSI bit enable, so will need to think through that some more (assuming I am not missing anything from the details you have provided).

Meanwhile can you please provide some more inputs on the following questions

1) What is the device speed?

2) Did lowering the baud rate reduce the frequency of the failure or eliminate the failure?

3) When the INTID is being read back as 0x0 , what is the status of the IPEND bit in the IIR register (is it set or clear)?

4) Would it be possible for you to snapshot your entire UART ISR code for us to review , to make sure we are not missing something, in how you would need to construct the ISR to handle situation where you could simultaneously be getting a transmit empty interrupt for data transmitted from C6747 as well as receiving bytes from the PC side ( as you alluded this has a better possibility of hitting the condition of getting the simultaneous rx/tx interrupt condition as compared to internal/external loopback).

5) Can you tell me whether the FCR.DMAMODE1 bit is set or clear. If it is disabled, can you try your setup with this bit being enabled (note that this is a lower priority experiment)

NOTE: that if an UART interrupt source (RX Full) happens when other interrupt (TX Empty) is pending, the interrupt signal is not asserted for the interrupt. That is, UART sends only one interrupt to CPU even if there are multiple interrupts pending. So it is important to make use of IPEND bit IIR[0] in the ISR to ensure there are no extra pending interrupts before exiting the ISR.

On your point#5, the c6747 errata should not be impacting you unless you are making use of the CHIPINTn interrupts in your application. I am assuming you are not using those and if you were , you should be able to rule that out as the cause if you were to temporarily disable them and see its impact on your test setup. No other interrupts source (including UART) are impacted by this errata.

Regards

Mukul

0 Yoav Gold over 15 years ago in reply to Mukul Bhatnagar

Prodigy 250 points

Hi mukul, Answering your questions:

1. The device speed is 300Mhz

2.Lowering the Baud Rate (57600) didnt seem to make any difference (I'm not sure if it made it better or worst, But it happend).

3.IPend is 0x01 when I'm getting the Default interrupt (Not pending as I recall)

4. Ill paste the entire file at the end of this post (Init procedures + ISRs + TxTask). I just want to make sure you rememmber I'm Not working sith a Tx Empty interrupt,
I have a high priority task which send Data whenever he can (If there is data to send + THRE (or TEMT) says EMPTY)
And another thing, Our ISR (The HW interrupt handler invokes a SWI which calls the handling function) We did so in order for us to analize the tasks in the execution graph.
We suffer form the same symptom without it as well.

5.DMAMODE is disabled, I tried to enable it as well, Same results.

Hope this gives some clues,
Yoav.

The UART Driver file :

/******************************************* Includes *******************************************/

/* System includes */
#include "RevCcfg.h"
#include "Psc.h"
#include "cslr.h"
#include "csl_types.h"
#include "cslr_uart.h"
#include <cslr_syscfg_C6747.h>
#include <soc_C6747.h>
#include <hwi.h>
#include <c64.h>
#include <tsk.h>

/* SW includes */
#include "NewUart.h"

/******************************************* Externals *******************************************/
extern CSL_SyscfgRegsOvly BSW_t_SysRegs;
/******************************************* Static and Globals *******************************************/

static CSL_UartRegsOvly  BSW_t_Uart0Regs   = (CSL_UartRegsOvly)CSL_UART_0_REGS;
static CSL_UartRegsOvly  BSW_t_Uart1Regs      = (CSL_UartRegsOvly)CSL_UART_1_REGS;
static CSL_UartRegsOvly  BSW_t_Uart2Regs      = (CSL_UartRegsOvly)CSL_UART_2_REGS;

Uint8 UART_au8_RS232OutputBuffer[UART_BUFFERSIZE];
Uint8 UART_au8_RS232InputBuffer[UART_BUFFERSIZE];
Uint8 UART_au8_USBOutputBuffer[UART_BUFFERSIZE];
Uint8 UART_au8_USBInputBuffer[UART_BUFFERSIZE];
Uint8 UART_au8_GPSOutputBuffer[UART_BUFFERSIZE];
Uint8 UART_au8_GPSInputBuffer[UART_BUFFERSIZE];

/* Temporary Debug Globals */
Uint32 UART_u32_IrqCounter[NUM_OF_UARTS]        = {0,0,0};
Uint32 UART_u32_IrqProblemCounter[NUM_OF_UARTS] = {0,0,0};
Uint32 UART_u32_IrqRxCounterTO[NUM_OF_UARTS]    = {0,0,0};
Uint32 UART_u32_IrqRxCounterDR[NUM_OF_UARTS]    = {0,0,0};
Uint32 UART_u32_IrqTxCounter[NUM_OF_UARTS]      = {0,0,0};
Uint32 UART_u32_BytesReceived[NUM_OF_UARTS]     = {0,0,0};
Uint32 UART_u32_BytesSent[NUM_OF_UARTS]         = {0,0,0};
Uint32 UART_u32_DefaultCounter[NUM_OF_UARTS]    = {0,0,0};

Uint32 au32_DebugBuffer[20];
Uint8 u8_LineStatus = 0;

#define UART_COMPONENT_FIFO_SIZE 16

/******************************************* Functions *******************************************/

/***************************************************************************
--$(S
1. CSU Name:                   CSU#
2. CSU Purpose:
3. Input/Output Data Elements:
Input data elements:
  N/A
Output data elements:
  N/A
4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
N/A
--$)S
***************************************************************************/
void UART_F_NewInit()
{
UART_E_PortID e_PortID;
CSL_UartRegsOvly pt_RegSet;

UART_F_InitGlobals();
UART_F_InitSysRegs();
UART_F_InitBaudRate();
UART_F_InitFifo();
UART_F_InitComProtocol();
UART_F_DefineInterrupts();

/* enable transmitter and receiver (Reset and then enable) */
for(e_PortID = USB_UART_ID; e_PortID < NUM_OF_UARTS; e_PortID++)
{
  pt_RegSet = UART_at_ChannelDBTable[e_PortID].pt_RegSet;
  CSL_FINST(pt_RegSet->PWREMU_MGMT,UART_PWREMU_MGMT_UTRST,RESET);
  CSL_FINST(pt_RegSet->PWREMU_MGMT,UART_PWREMU_MGMT_UTRST,ENABLE);

CSL_FINST(pt_RegSet->PWREMU_MGMT,UART_PWREMU_MGMT_URRST,RESET);
CSL_FINST(pt_RegSet->PWREMU_MGMT,UART_PWREMU_MGMT_URRST,ENABLE);
}

return;
}
/***************************************************************************
--$(S
1. CSU Name:                   CSU#
2. CSU Purpose:
3. Input/Output Data Elements:
Input data elements:
  N/A
Output data elements:
  N/A
4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
N/A
--$)S
***************************************************************************/
void UART_F_DeviceInitUart0()
{
Psc_ModuleClkCtrl(Psc_DevId_0, PSC_UART0_LPSC, TRUE);

return;
}
/***************************************************************************/
void UART_F_DeviceInitUart1()
{
Psc_ModuleClkCtrl(Psc_DevId_1, PSC_UART1_LPSC, TRUE);

return;
}
/***************************************************************************/
void UART_F_DeviceInitUart2()
{
Psc_ModuleClkCtrl(Psc_DevId_1, PSC_UART2_LPSC, TRUE);

return;
}
/***************************************************************************
--$(S
1. CSU Name: UART_F_InitChannelDBTable       CSU#
2. CSU Purpose:
   Init the Channel DB table
3. Input/Output Data Elements:
Input data elements:
  None
Output data elements:
  None
4. Algorithm & Logic Flow:
  None
5. Error Handling & Limitations:
  None
--$)S
***************************************************************************/
void UART_F_InitGlobals()
{
/* Init Global buffer */
memset( UART_au8_RS232OutputBuffer  , 0, UART_BUFFERSIZE*sizeof(Uint8) );
memset( UART_au8_USBOutputBuffer   , 0, UART_BUFFERSIZE*sizeof(Uint8) );
memset( UART_au8_GPSOutputBuffer   , 0, UART_BUFFERSIZE*sizeof(Uint8) );
memset( UART_au8_GPSInputBuffer        , 0, UART_BUFFERSIZE*sizeof(Uint8) );
memset( UART_au8_RS232InputBuffer      , 0, UART_BUFFERSIZE*sizeof(Uint8) );
memset( UART_au8_USBInputBuffer        , 0, UART_BUFFERSIZE*sizeof(Uint8) );

UART_F_InitChannelDBTable();
return;
}
/***************************************************************************
--$(S
1. CSU Name: UART_F_InitChannelDBTable       CSU#
2. CSU Purpose:
   Init the Channel DB table
3. Input/Output Data Elements:
Input data elements:
  None
Output data elements:
  None
4. Algorithm & Logic Flow:
  None
5. Error Handling & Limitations:
  None
--$)S
***************************************************************************/
void   UART_F_InitChannelDBTable()
{
Uint32 i;

/* Set Channel table */
memset(UART_at_ChannelDBTable[GPS_UART_ID].Indexes[0] , 0, NUM_OF_FIFO_OPS*sizeof(Uint16) );
memset(UART_at_ChannelDBTable[GPS_UART_ID].Indexes[1] , 0, NUM_OF_FIFO_OPS*sizeof(Uint16) );
UART_at_ChannelDBTable[GPS_UART_ID].Buffer[FIFO_TX] = UART_au8_GPSOutputBuffer;
UART_at_ChannelDBTable[GPS_UART_ID].Buffer[FIFO_RX] = UART_au8_GPSInputBuffer;
UART_at_ChannelDBTable[GPS_UART_ID].u32_CycBuffersize = UART_BUFFERSIZE;
UART_at_ChannelDBTable[GPS_UART_ID].pt_RegSet = BSW_t_Uart1Regs;

memset(UART_at_ChannelDBTable[USB_UART_ID].Indexes[0] , 0, NUM_OF_FIFO_OPS*sizeof(Uint16) );
memset(UART_at_ChannelDBTable[USB_UART_ID].Indexes[1] , 0, NUM_OF_FIFO_OPS*sizeof(Uint16) );
UART_at_ChannelDBTable[USB_UART_ID].Buffer[FIFO_TX] = UART_au8_USBOutputBuffer;
UART_at_ChannelDBTable[USB_UART_ID].Buffer[FIFO_RX] = UART_au8_USBInputBuffer;
UART_at_ChannelDBTable[USB_UART_ID].u32_CycBuffersize = UART_BUFFERSIZE;
UART_at_ChannelDBTable[USB_UART_ID].pt_RegSet = BSW_t_Uart0Regs;

memset(UART_at_ChannelDBTable[RS232_UART_ID].Indexes[0], 0, NUM_OF_FIFO_OPS*sizeof(Uint16));
memset(UART_at_ChannelDBTable[RS232_UART_ID].Indexes[1], 0, NUM_OF_FIFO_OPS*sizeof(Uint16));
UART_at_ChannelDBTable[RS232_UART_ID].Buffer[FIFO_TX] = UART_au8_RS232OutputBuffer;
UART_at_ChannelDBTable[RS232_UART_ID].Buffer[FIFO_RX] = UART_au8_RS232InputBuffer;
UART_at_ChannelDBTable[RS232_UART_ID].u32_CycBuffersize = UART_BUFFERSIZE;
UART_at_ChannelDBTable[RS232_UART_ID].pt_RegSet = BSW_t_Uart2Regs;

5. Error Handling & Limitations:
N/A
--$)S
***************************************************************************/
void UART_F_InitSysRegs()
{
BSW_t_SysRegs->KICK0R = 0x83e70b13;
BSW_t_SysRegs->KICK1R = 0x95A4F1E0;
BSW_t_SysRegs->CFGCHIP0 = CSL_FMKT(SYSCFG_CFGCHIP0_PLL_MASTER_LOCK, FREE);

/* For UART 0 */
CSL_FINST(BSW_t_SysRegs->PINMUX8, SYSCFG_PINMUX8_PINMUX8_15_12, UART0_RXD);
CSL_FINST(BSW_t_SysRegs->PINMUX8, SYSCFG_PINMUX8_PINMUX8_19_16, UART0_TXD);

/* For UART 1 */
CSL_FINST(BSW_t_SysRegs->PINMUX11, SYSCFG_PINMUX11_PINMUX11_11_8, UART1_RXD);
CSL_FINST(BSW_t_SysRegs->PINMUX11, SYSCFG_PINMUX11_PINMUX11_15_12, UART1_TXD);

/* For UART 2 */
CSL_FINST(BSW_t_SysRegs->PINMUX8, SYSCFG_PINMUX8_PINMUX8_31_28, UART2_RXD);
CSL_FINST(BSW_t_SysRegs->PINMUX9, SYSCFG_PINMUX9_PINMUX9_3_0, UART2_TXD);
}
/***************************************************************************
--$(S
1. CSU Name:                   CSU#
2. CSU Purpose:
3. Input/Output Data Elements:
Input data elements:
  N/A
Output data elements:
  N/A
4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
N/A
--$)S
***************************************************************************/
void UART_F_InitBaudRate()
{

UART_E_PortID e_PortID;
CSL_UartRegsOvly pt_RegSet;

for(e_PortID = USB_UART_ID; e_PortID < NUM_OF_UARTS; e_PortID++)
{
pt_RegSet = UART_at_ChannelDBTable[e_PortID].pt_RegSet;

  /* Define the sampling rate
   * Using this sampling rate, you can define the baudrate according to this :
   * DIVISOR = "UART input clock" / Desired Baudrate*Sampling
   * */
  CSL_FINST(pt_RegSet->MDR, UART_MDR_OSM_SEL, 13XOVERSAMPLING);

/* Allow access to the divisor latch */
CSL_FINST(pt_RegSet->LCR, UART_LCR_DLAB, ENABLE);

  /* Set the divisor High and Low Bytes */
  CSL_FINS(pt_RegSet->DLH, UART_DLH_DLH, UART_DIVISOR_FOR_115200_x13SAMPLING >> 8);
  CSL_FINS(pt_RegSet->DLL, UART_DLL_DLL, UART_DIVISOR_FOR_115200_x13SAMPLING & 0x00FF);
}

return;
}

5. Error Handling & Limitations:
N/A
--$)S
***************************************************************************/
void UART_F_InitFifo()
{
UART_E_PortID e_PortID;
CSL_UartRegsOvly pt_RegSet;

for(e_PortID = USB_UART_ID; e_PortID < NUM_OF_UARTS; e_PortID++)
{
  pt_RegSet = UART_at_ChannelDBTable[e_PortID].pt_RegSet;
  /* Enable the Fifo */
  CSL_FINST(pt_RegSet->FCR, UART_FCR_FIFOEN, ENABLE);

  /* Clear Both fifos */
  CSL_FINST(pt_RegSet->FCR, UART_FCR_RXCLR, CLR);
  CSL_FINST(pt_RegSet->FCR, UART_FCR_TXCLR, CLR);

  /* Disable DMA */
  CSL_FINST(pt_RegSet->FCR, UART_FCR_DMAMODE1, DISABLE);
  /* Receiver FIFO trigger level */
   /*
   RXFIFTL sets the trigger level for the receiver FIFO. When the trigger level
   is reached, a receiver data-ready interrupt is generated (if the interrupt request is enabled). Once the
   FIFO drops below the trigger level, the interrupt is cleared.
  */
  CSL_FINST(pt_RegSet->FCR, UART_FCR_RXFIFTL, CHAR1);
}

5. Error Handling & Limitations:
N/A
--$)S
***************************************************************************/
void UART_F_InitComProtocol()
{
UART_E_PortID e_PortID;
CSL_UartRegsOvly pt_RegSet;

for(e_PortID = USB_UART_ID; e_PortID < NUM_OF_UARTS; e_PortID++)
{
  pt_RegSet = UART_at_ChannelDBTable[e_PortID].pt_RegSet;
  CSL_FINST(pt_RegSet->LCR, UART_LCR_WLS, 8BITS);
  CSL_FINST(pt_RegSet->LCR, UART_LCR_STB, 1BIT);
  CSL_FINST(pt_RegSet->LCR, UART_LCR_EPS, EVEN);
  CSL_FINST(pt_RegSet->LCR, UART_LCR_PEN, DISABLE);
  CSL_FINST(pt_RegSet->LCR, UART_LCR_SP , DISABLE);
  CSL_FINST(pt_RegSet->LCR, UART_LCR_BC , DISABLE);

  /* modem control register */
  pt_RegSet->MCR = CSL_FMKT(UART_MCR_RTS,DISABLE)       /* RTS control       */
          | CSL_FMKT(UART_MCR_LOOP,DISABLE) /* loopback mode */
          | CSL_FMKT(UART_MCR_AFE,DISABLE); /* auto flow enable */

}

5. Error Handling & Limitations:
N/A
--$)S
***************************************************************************/
void UART_F_DefineInterrupts()
{
UART_E_PortID e_PortID;
CSL_UartRegsOvly pt_RegSet;

for(e_PortID = USB_UART_ID; e_PortID < NUM_OF_UARTS; e_PortID++)
{
  pt_RegSet = UART_at_ChannelDBTable[e_PortID].pt_RegSet;
  /* Allows access to the receiver buffer register (RBR), the transmitter holding register (THR), and the
   interrupt enable register (IER) selected. At the address shared by RBR, THR, and DLL, the CPU can
   read from RBR and write to THR. At the address shared by IER and DLH, the CPU can read from and
   write to IER. */
  CSL_FINS(pt_RegSet->LCR, UART_LCR_DLAB, 0);
  CSL_FINST(pt_RegSet->PWREMU_MGMT, UART_PWREMU_MGMT_FREE, STOP);

  pt_RegSet->IER = CSL_FMKT(UART_IER_EDSSI, DISABLE )       /* Modem Status */
         |   CSL_FMKT(UART_IER_ELSI , ENABLE )    /* Line Status */
         |   CSL_FMKT(UART_IER_ETBEI, DISABLE )   /* Tx IRQ       */
         |   CSL_FMKT(UART_IER_ERBI , ENABLE);   /* Rx IRQ       */

}

C64_enableIER(C64_EINT4 | C64_EINT5 | C64_EINT6);

5. Error Handling & Limitations:
N/A
--$)S
***************************************************************************/
void UART_F_Uart0IrqHandle(Uint32 u32_Param)
{
UART_u32_IrqCounter[u32_Param]++;
SWI_post(&Swi_Uart0Rx);

return;
}
/***************************************************************************/
void UART_F_Uart1IrqHandle(Uint32 u32_Param)
{
UART_u32_IrqCounter[u32_Param]++;
SWI_post(&Swi_Uart1Rx);

return;
}
/***************************************************************************/
void UART_F_Uart2IrqHandle(Uint32 u32_Param)
{
UART_u32_IrqCounter[u32_Param]++;
SWI_post(&Swi_Uart2Rx);

5. Error Handling & Limitations:
N/A
--$)S
***************************************************************************/
void UART_F_SwiUart0RxHandler()
{
UART_F_UartRxHandler(USB_UART_ID);
return;
}
/***************************************************************************/
void UART_F_SwiUart1RxHandler()
{
UART_F_UartRxHandler(GPS_UART_ID);
return;
}
/***************************************************************************/
void UART_F_SwiUart2RxHandler()
{
UART_F_UartRxHandler(RS232_UART_ID);
return;
}
/***************************************************************************
--$(S
1. CSU Name:                   CSU#
2. CSU Purpose:
3. Input/Output Data Elements:
Input data elements:
  N/A
Output data elements:
  N/A
4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
N/A
--$)S
***************************************************************************/
void UART_F_UartRxHandler(UART_E_PortID e_PortID)
{
UART_E_IrqType e_IrqType;
CSL_UartRegsOvly pt_CurrRegSet;
Uint8 u8_IPend = 0, u8_LineStatus;

pt_CurrRegSet = UART_at_ChannelDBTable[e_PortID].pt_RegSet;

e_IrqType = (UART_E_IrqType)CSL_FEXT(pt_CurrRegSet->IIR, UART_IIR_INTID);
switch(e_IrqType)
{
  case ITY_LineStatus   :
   UART_u32_IrqProblemCounter[e_PortID]++;
   u8_LineStatus = (BSW_t_Uart2Regs->LSR & 0x00FF);
   break;
  case ITY_RecDataReady :
   UART_u32_IrqRxCounterDR[e_PortID]++;
   UART_F_ReadReceiveDataBuffer(e_PortID);
   break;
  case ITY_RecTimeOut   :
   UART_u32_IrqRxCounterTO[e_PortID]++;
   UART_F_ReadReceiveDataBuffer(e_PortID);
   break;
  case ITY_TxHoldEmpty :
   UART_F_SendTxFifo(e_PortID);
   UART_u32_IrqTxCounter[e_PortID]++;
   break;
  default:
   UART_u32_DefaultCounter[e_PortID]++;
   u8_IPend      = CSL_FEXT(pt_CurrRegSet->IIR, UART_IIR_IPEND);
   u8_LineStatus = (BSW_t_Uart2Regs->LSR & 0x00FF);
   break;
}

5. Error Handling & Limitations:
N/A
--$)S
***************************************************************************/
void UART_F_ReadReceiveDataBuffer(UART_E_PortID e_PortID)
{
CSL_UartRegsOvly pt_CurrRegSet;
Uint8 *pu8_RecBuffer ;
Uint16 u16_WriteIndex;
Uint32 u32_BufferSize;
Uint32 u32_HwiStatus;
static Uint8 u8_RecData = 0, u8_DCounter = 0;

pt_CurrRegSet    = UART_at_ChannelDBTable[e_PortID].pt_RegSet;
pu8_RecBuffer    = UART_at_ChannelDBTable[e_PortID].Buffer[FIFO_RX];
u16_WriteIndex = UART_at_ChannelDBTable[e_PortID].Indexes[FIFO_RX][WRITE_INDEX];
u32_BufferSize   = UART_at_ChannelDBTable[e_PortID].u32_CycBuffersize;

while(CSL_FEXT(pt_CurrRegSet->LSR, UART_LSR_DR) == CSL_UART_LSR_DR_READY)
{
  UART_u32_BytesReceived[e_PortID]++;
  pu8_RecBuffer[u16_WriteIndex] = CSL_FEXT(pt_CurrRegSet->RBR, UART_RBR_DATA);
  u16_WriteIndex = ((u16_WriteIndex + 1) % u32_BufferSize);
}

UART_at_ChannelDBTable[e_PortID].Indexes[FIFO_RX][WRITE_INDEX] = u16_WriteIndex;

5. Error Handling & Limitations:
N/A
--$)S
***************************************************************************/
Bool UART_F_SendData(UART_E_PortID e_PortID, Uint8 *pu8_buffer, Uint16 u16_Length)
{
Bool b_RetVal = TRUE;
Uint8 *pu8_DataSource = pu8_buffer;
CSL_UartRegsOvly pt_CurrRegSet = UART_at_ChannelDBTable[e_PortID].pt_RegSet;
Uint8 *pu8_DataDest         = UART_at_ChannelDBTable[e_PortID].Buffer[FIFO_TX];
Uint16 u16_WriteIndex         = UART_at_ChannelDBTable[e_PortID].Indexes[FIFO_TX][WRITE_INDEX];
Uint16 u16_ReadIndex         = UART_at_ChannelDBTable[e_PortID].Indexes[FIFO_TX][READ_INDEX];
Uint32 u32_CycBuffSize         = UART_at_ChannelDBTable[e_PortID].u32_CycBuffersize;
Uint16 u16_VirtualReadIndex;

if(u16_ReadIndex <= u16_WriteIndex)
{
u16_VirtualReadIndex = u16_ReadIndex + u32_CycBuffSize;

}
else
{
u16_VirtualReadIndex = u16_ReadIndex;
}

if((u16_WriteIndex + u16_Length) >= u16_VirtualReadIndex)
{
return FALSE;
}

while(u16_Length--)
{
  *(pu8_DataDest+u16_WriteIndex) = *pu8_DataSource;
  pu8_DataSource++;
  u16_WriteIndex = (u16_WriteIndex + 1) % u32_CycBuffSize;
}

UART_at_ChannelDBTable[e_PortID].Indexes[FIFO_TX][WRITE_INDEX] = u16_WriteIndex;

return b_RetVal;
}
/***************************************************************************
--$(S
1. CSU Name:                   CSU#
2. CSU Purpose:
3. Input/Output Data Elements:
Input data elements:
  N/A
Output data elements:
  N/A
4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
N/A
--$)S
***************************************************************************/
void UART_F_SendTxFifo(UART_E_PortID e_PortID)
{
Uint8 u8_i, *pu8_DataSource;
Uint16 u16_ReadIndex, u16_WriteIndex, u16_VirtualWriteIndex, u16_len;
Uint32 u32_CycBufSize, u32_HwiStatus;
CSL_UartRegsOvly pt_CurrRegSet;

pu8_DataSource = UART_at_ChannelDBTable[e_PortID].Buffer[FIFO_TX];
u16_WriteIndex = UART_at_ChannelDBTable[e_PortID].Indexes[FIFO_TX][WRITE_INDEX];
u16_ReadIndex = UART_at_ChannelDBTable[e_PortID].Indexes[FIFO_TX][READ_INDEX];
u32_CycBufSize = UART_at_ChannelDBTable[e_PortID].u32_CycBuffersize;
pt_CurrRegSet = UART_at_ChannelDBTable[e_PortID].pt_RegSet;
u8_i = 0;

/* Find out how many bytes are there to send */
if(u16_WriteIndex < u16_ReadIndex )
{
u16_VirtualWriteIndex = u16_WriteIndex + u32_CycBufSize;
}
else
{
u16_VirtualWriteIndex = u16_WriteIndex;
}
u16_len = u16_VirtualWriteIndex - u16_ReadIndex;

/* Wait for Tx Fifo Empty flag */
if(CSL_FEXT(pt_CurrRegSet->LSR, UART_LSR_TEMT) == CSL_UART_LSR_TEMT_EMPTY)
{
  //u32_HwiStatus = HWI_disable();
  /* Limiting # of bytes to send */
  while( (u8_i < UART_COMPONENT_FIFO_SIZE) && (u8_i < u16_len) )
  {
   /* Indication */
   UART_u32_BytesSent[e_PortID]++;

/* Tx the Byte */
CSL_FINS(pt_CurrRegSet->THR, UART_THR_DATA, pu8_DataSource[u16_ReadIndex]);

/* "Yaanu" Tx the Byte (Write to Scratch pad)*/
//CSL_FINS(pt_CurrRegSet->SCR, UART_SCR_SCR, pu8_DataSource[u16_ReadIndex]);

   /* Update Local Counters */
   u8_i++;
   u16_ReadIndex = ((u16_ReadIndex + 1) % u32_CycBufSize);
  }

UART_at_ChannelDBTable[e_PortID].Indexes[FIFO_TX][READ_INDEX] = u16_ReadIndex;
}

return;
}
/***************************************************************************
--$(S
1. CSU Name: CSU#
2. CSU Purpose:

3. Input/Output Data Elements:
Input data elements:

Output data elements:

4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
N/A
--$)S
***************************************************************************/
void UART_F_TxTsk()
{
UART_E_PortID e_PortID;

SEM_pend(&SEM_Tx, SYS_FOREVER);
while(1)
{
  for(e_PortID = USB_UART_ID; e_PortID < NUM_OF_UARTS; e_PortID++)
  {
   UART_F_SendTxFifo(e_PortID);
  }
  TSK_sleep(1);
}

}

0 Mukul Bhatnagar over 15 years ago in reply to Yoav Gold

TI__Guru* 84325 points

Hi Yoav

We spent some time browsing through your code snippets, I think your UART event handler code is still not robust enough , to address the NOTE I put in the previous post. You need make sure that IPEND bit is polled for before exiting the ISR, so I recommend

1) At least for initial debug/resolution , not go through route of posting a SWI in your IRQ handler (have the relevant handling function in the HWI handler itself).

2) I am pasting the snippet of code from the PSP release for the UART handler --> I would recommend you follow this as much as possible in your version of the implementation. The key thing being the while loop highlighted in bold.

3) Try to map the UART interrupt to one of the direct HWI , rather then going through the ECM dispatcher (and if you continue to use the ECM dispatcher, then definitely ensure that all other interrupts are masked). This is lower priority compared to 1 & 2.

Hope this helps.

---

void uartIsr(Arg arg)

{

volatile Uint32 status = 0x01u;

Uint32 intrCnt = 0;

Uart_Object *instHandle = NULL;

Uart_ChanObj *chanHandle = NULL;

Uint32 xfer = 0;

#ifdef BIOS_PWRM_ENABLE

Uns count = 0x00;

#else

IOM_Packet *ioPacket = NULL;

#endif

assert(NULL != arg);

instHandle = (Uart_Object*)arg;

status = (Uint32)uartGetIntrStatus(instHandle);

while ((CSL_UART_IIR_IPEND_PEND == (status & CSL_UART_IIR_IPEND_NO_PEND))

&& ((intrCnt) < (Uart_MAX_ISR_LOOP)))

{

intrCnt++;

/* check for any line error while transfer */

if (CSL_UART_IIR_INTID_RLS ==

(CSL_UART_IIR_INTID_RLS & (status >> CSL_UART_IIR_INTID_SHIFT)))

{

/* call this function when ther is any line error */

uartHandleRxError(&(instHandle->rcvChanObj));

}

else if(Uart_OpMode_INTERRUPT == instHandle->opMode)

{

/* check whether any character timeout happened */

if( CSL_UART_IIR_INTID_RDA ==

(CSL_UART_IIR_INTID_RDA & (status >> CSL_UART_IIR_INTID_SHIFT)))

{

if(CSL_UART_IIR_INTID_CTI ==

(CSL_UART_IIR_INTID_CTI & (status >> CSL_UART_IIR_INTID_SHIFT)))

{

chanHandle = &(instHandle->rcvChanObj);

/* if timeout error then update stats */

instHandle->stats.rxTimeout++;

/* Increment the error count */

chanHandle->errors++;

/* Update the IOP with proper status */

chanHandle->activeIOP->status = IOM_ETIMEOUT;

/* Transfer the remanant bytes if any are remaining in the*

* FIFO */

xfer = uartFifoRead(chanHandle,

chanHandle->activeBuf,

chanHandle->bytesRemaining);

chanHandle->bytesRemaining -= xfer;

chanHandle->activeBuf += xfer;

instHandle->stats.rxBytes += xfer;

/* Disable the RX interrupts before completing. If only *

* there is a packet for processing it shall be re-enabled*/

uartIntrDisable(instHandle,

(Uint32)(Uart_Intr_RLS | Uart_Intr_RHR));

/* Perform the operation to complete the IO */

Uart_localCompleteCurrentIO(chanHandle);

#ifdef BIOS_PWRM_ENABLE

if ((TRUE == instHandle->devParams.pscPwrmEnable) &&

(TRUE == instHandle->pwrmInfo.ioSuspend))

{

/* set the current active IOP as NULL */

chanHandle->activeIOP = NULL;

instHandle->devState = Uart_DriverState_PWRM_SUSPEND;

if ((NULL == instHandle->rcvChanObj.activeIOP) &&

(NULL == instHandle->xmtChanObj.activeIOP))

{

/* if both the channels are inactive then reset *

* the io suspend flag */

instHandle->pwrmInfo.ioSuspend = FALSE;

if ((PWRM_GOINGTOSLEEP == instHandle->pwrmInfo.pwrmEvent) ||

(PWRM_GOINGTODEEPSLEEP == instHandle->pwrmInfo.pwrmEvent))

{

/* reduce the dependency count */

status = PWRM_getDependencyCount(

(PWRM_Resource)instHandle->deviceInfo.pwrmLpscId,

&count);

instHandle->pwrmInfo.dependencyCount = count;

if (PWRM_SOK == status)

{

while (count > 0)

{

status = PWRM_releaseDependency(

(PWRM_Resource)

instHandle->deviceInfo.pwrmLpscId);

if (PWRM_SOK != status)

{

break;

}

count--;

}

/* call the delayed completion function */

(instHandle->pwrmInfo.delayedCompletionFxn \

[instHandle->pwrmInfo.pwrmEvent])();

}

#else

/* Now that we have just completed the current IOP *

* we proceed to check if there are still packets *

* pending in pending queue */

if (FALSE == QUE_empty(&(chanHandle->queuePendingList)))

{

/* we have atleast one packet */

ioPacket = (IOM_Packet *)QUE_get(&(chanHandle->queuePendingList));

/* validate and update the iop */

if (NULL != ioPacket)

{

chanHandle->activeIOP = ioPacket;

chanHandle->activeBuf = ioPacket->addr;

chanHandle->bytesRemaining = ioPacket->size;

chanHandle->errors = 0;

}

uartIntrEnable(instHandle,

(Uint32)(Uart_Intr_RLS | Uart_Intr_RHR));

}

else

{

chanHandle->activeIOP = NULL;

}

#endif

}

else

{

/* Disable the receive interrupt until current interrupt *

* is processed. Re-enabled again in uartIntrHandler() */

uartIntrDisable(instHandle,(Uint32)(Uart_Intr_RHR));

SWI_post(instHandle->rxTskletHandle);

}

else

{

/* check whether Tx register is empty or not */

if (CSL_UART_IIR_INTID_THRE ==

(CSL_UART_IIR_INTID_THRE & (status >> CSL_UART_IIR_INTID_SHIFT)))

{

/* Disable the transmit interrupt until current interrupt *

* is processed. Re-enabled again in uartIntrHandler() */

uartIntrDisable(instHandle,(Uint32)(Uart_Intr_THR));

SWI_post(instHandle->txTskletHandle);

}

else

{

/* check modem status */

if (CSL_UART_IIR_INTID_MODSTAT ==

(CSL_UART_IIR_INTID_MODSTAT & (status >> CSL_UART_IIR_INTID_SHIFT)))

{

/* Read the MSR to clear Modem Status Int cause */

(instHandle->deviceInfo.baseAddress)->SCR =

(instHandle->deviceInfo.baseAddress)->MSR;

}

else

{

/* Do nothing */

}

status = uartGetIntrStatus(instHandle);

}

0 Yoav Gold over 15 years ago in reply to Mukul Bhatnagar

Prodigy 250 points

Hi mukul,

Well, I added a mechanizem that will gurantee that I dont leave the ISR while I still have a pending interrupt (I added a do-while loop over my switch-case) and now I run the handling function from the ISR and not the SWI.
This resulted in the same manner as before (receiving an unidentified interrupt every once in a while when I'm using Read&Write simultaneously).

In addition, I'm not using the ECM dispatcher...my interrupts are listed as HWI, that is, in my .tcf file, I have written the UART event number (i.e event number 69 for UART2) under a specific interrupt (i.e, interrupt 4).I marked the "use dispatcher" check Box, and I'm using "Mask all".

I'm pasting my .tcf file down here...maybe it can assist in something

Thanks again,

Yoav

/* Load platform file for evm6747 */
utils.loadPlatform("ti.platforms.evm6747");

/* Enable Time Stamp Logging */
bios.LOG.TS = true;

/* Enable common BIOS features used by all examples */
bios.enableRealTimeAnalysis(prog);
bios.enableMemoryHeaps(prog);
bios.enableRtdx(prog);
bios.enableTskManager(prog);
bios.setMemCodeSections(prog, prog.get("SDRAM"));

/* Enable ECM Handler */
bios.ECM.ENABLE = 1;

/* Import driver TCI files */
utils.importFile("RevC.tci");

/*
* Enable heap usage.
*/
bios.MEM.instance("SDRAM").createHeap = 1;
bios.MEM.instance("SDRAM").heapSize = 0x4000;
bios.MEM.BIOSOBJSEG = prog.get("SDRAM");
bios.MEM.MALLOCSEG = prog.get("SDRAM");

/* setup LOGs */
bios.LOG_system.bufSeg = prog.get("IRAM");
bios.LOG_system.bufLen = 1024;
bios.LOG_system.logType = "circular";

bios.LOG.create("trace");
bios.LOG.instance("trace").bufLen = 1024;
bios.LOG.instance("trace").bufSeg = prog.get("IRAM");

bios.LOG.create("DVTEvent_Log");
bios.LOG.instance("DVTEvent_Log").bufSeg = prog.get("IRAM");
bios.LOG.instance("DVTEvent_Log").bufLen = 8192;
bios.LOG.instance("DVTEvent_Log").comment = "DVT";

/* Allow DSP to reset timer */
bios.CLK.RESETTIMER = 1;

/* Use instrumented bios libraries */
bios.GBL.ENABLEINST = 1;

/* MAR bits config */
bios.GBL.C64PLUSMAR128to159 = 0x0000ffff;

/* ECM configuration */
bios.HWI.instance("HWI_INT7").interruptSelectNumber = 0;
bios.HWI.instance("HWI_INT8").interruptSelectNumber = 1;
bios.HWI.instance("HWI_INT9").interruptSelectNumber = 2;
bios.HWI.instance("HWI_INT10").interruptSelectNumber = 3;

/*task configuration*/
bios.TSK.create("echoTask");
bios.TSK.instance("echoTask").stackSize = 16384;
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").comment = "Sample Application";

/* system stack size */
bios.MEM.STACKSIZE = 0x10000;

bios.LOG.instance("trace").bufLen = 2048;
bios.LOG.instance("trace").bufLen = 8192;
bios.LOG.instance("trace").bufLen = 4096;
bios.MEM.NOMEMORYHEAPS = 1;
bios.MEM.BIOSSEG = prog.get("IRAM");
bios.MEM.SYSINITSEG = prog.get("IRAM");
bios.MEM.HWISEG = prog.get("IRAM");
bios.MEM.HWIVECSEG = prog.get("IRAM");
bios.MEM.RTDXTEXTSEG = prog.get("IRAM");
bios.MEM.TEXTSEG = prog.get("IRAM");
bios.MEM.TEXTSEG = prog.get("L3_CBA_RAM");
bios.MEM.OBJSEG = prog.get("SDRAM");
bios.MEM.ARGSSEG = prog.get("SDRAM");
bios.MEM.STACKSEG = prog.get("SDRAM");
bios.MEM.GBLINITSEG = prog.get("SDRAM");
bios.MEM.TRCDATASEG = prog.get("SDRAM");
bios.MEM.SYSDATASEG = prog.get("SDRAM");
bios.MEM.ARGSSEG = prog.get("L3_CBA_RAM");
bios.MEM.STACKSEG = prog.get("L3_CBA_RAM");
bios.MEM.GBLINITSEG = prog.get("L3_CBA_RAM");
bios.MEM.TRCDATASEG = prog.get("L3_CBA_RAM");
bios.MEM.SYSDATASEG = prog.get("L3_CBA_RAM");
bios.MEM.OBJSEG = prog.get("L3_CBA_RAM");
bios.MEM.STACKSEG = prog.get("IRAM");
bios.MEM.STACKSEG = prog.get("L3_CBA_RAM");
bios.MEM.TEXTSEG = prog.get("IRAM");
bios.MEM.TEXTSEG = prog.get("L3_CBA_RAM");
bios.MEM.OBJSEG = prog.get("SDRAM");
bios.MEM.STACKSIZE = 0x0400;
bios.MEM.OBJSEG = prog.get("L3_CBA_RAM");
bios.MEM.STACKSIZE = 0x0800;
bios.MEM.NOMEMORYHEAPS = 0;
bios.MEM.instance("L3_CBA_RAM").createHeap = 1;
bios.MEM.instance("L3_CBA_RAM").enableHeapLabel = 0;
bios.MEM.MALLOCSEG = prog.get("L3_CBA_RAM");
bios.MEM.BIOSOBJSEG = prog.get("L3_CBA_RAM");
bios.MEM.instance("L3_CBA_RAM").heapSize = 0x00000800;
bios.MEM.STACKSIZE = 0x1000;
bios.MEM.NOMEMORYHEAPS = 1;
bios.TSK.instance("echoTask").stackMemSeg = prog.get("L3_CBA_RAM");
bios.TSK.instance("echoTask").stackSize = 1000;
bios.MEM.STACKSIZE = 0x0800;
bios.MEM.NOMEMORYHEAPS = 0;
bios.MEM.NOMEMORYHEAPS = 1;
bios.TSK.instance("echoTask").stackMemSeg = prog.get("IRAM");
bios.MEM.STACKSEG = prog.get("IRAM");
bios.MEM.TEXTSEG = prog.get("SDRAM");
bios.MEM.TEXTSEG = prog.get("IRAM");
bios.MEM.TEXTSEG = prog.get("L3_CBA_RAM");
bios.MEM.TEXTSEG = prog.get("SDRAM");
bios.MEM.TEXTSEG = prog.get("L3_CBA_RAM");
bios.MEM.TEXTSEG = prog.get("SDRAM");
bios.MEM.BIOSSEG = prog.get("SDRAM");
bios.MEM.TEXTSEG = prog.get("L3_CBA_RAM");
bios.MEM.FARSEG = prog.get("SDRAM");
bios.MEM.CINITSEG = prog.get("SDRAM");
bios.MEM.instance("SDRAM").len = 0x01000000;
bios.MEM.instance("SDRAM").comment = "16Mbytes of the DSP's off-chip memory";
bios.MEM.BIOSSEG = prog.get("IRAM");
bios.MEM.FARSEG = prog.get("IRAM");
bios.MEM.CINITSEG = prog.get("IRAM");
bios.MEM.TEXTSEG = prog.get("IRAM");
bios.MEM.TEXTSEG = prog.get("L3_CBA_RAM");
bios.MEM.CINITSEG = prog.get("L3_CBA_RAM");
bios.MEM.CINITSEG = prog.get("IRAM");
bios.MEM.GBLINITSEG = prog.get("IRAM");
bios.MEM.create("FLASH");
bios.MEM.instance("FLASH").comment = "External Flash";
bios.MEM.instance("FLASH").base = 0x90000000;
bios.MEM.instance("FLASH").len = 0x00ffffff;
bios.MEM.instance("FLASH").base = 0x60000000;
bios.MEM.TEXTSEG = prog.get("SDRAM");
bios.MEM.instance("IRAM").base = 0x11805900;
bios.MEM.instance("IRAM").len = 0x00020000;
bios.MEM.create("IRAM_DATA");
bios.MEM.instance("IRAM_DATA").base = 0x11825900;
bios.MEM.instance("IRAM_DATA").len = 0x0001a700;
bios.MEM.instance("IRAM_DATA").space = "code/data";
bios.MEM.create("Boot_Sig_Sec");
bios.MEM.instance("Boot_Sig_Sec").base = 0x11802800;
bios.MEM.instance("Boot_Sig_Sec").len = 0x00000014;
bios.MEM.create("Boot_C_Sec");
bios.MEM.instance("Boot_C_Sec").base = 0x11800060;
bios.MEM.instance("Boot_C_Sec").len = 0x000003a0;
bios.MEM.create("Boot_C_Next_Sec");
bios.MEM.instance("Boot_C_Next_Sec").base = 0x11800400;
bios.MEM.instance("Boot_C_Next_Sec").len = 0x00002400;
bios.MEM.instance("Boot_C_Next_Sec").comment = "9 kbyte ofnext code";
bios.MEM.instance("Boot_Sig_Sec").space = "code";
bios.MEM.instance("Boot_C_Sec").space = "code";
bios.MEM.instance("Boot_C_Next_Sec").space = "code";
bios.MEM.create("Boot_Asm_Sec");
bios.MEM.instance("Boot_Asm_Sec").base = 0x11805900;
bios.MEM.instance("Boot_Asm_Sec").comment = "boot asm part";
bios.MEM.instance("Boot_Asm_Sec").len = 0x00000060;
bios.MEM.instance("Boot_Asm_Sec").base = 0x11800000;
bios.MEM.FARSEG = prog.get("IRAM_DATA");
bios.MEM.create("Cint00_Call_Sec");
bios.MEM.instance("Cint00_Call_Sec").base = 0x11805814;
bios.MEM.instance("Cint00_Call_Sec").len = 0x000000ec;
bios.MEM.instance("Cint00_Call_Sec").space = "code/data";
bios.MEM.instance("SDRAM").base = 0xc0000060;
bios.MEM.instance("SDRAM").len = 0x107fffa0;
bios.MEM.TEXTSEG = prog.get("IRAM");
bios.MEM.instance("SDRAM").base = 0xc0000000;
bios.MEM.instance("SDRAM").len = 0x01000000;
bios.MEM.create("STACK");
bios.MEM.instance("STACK").base = 0x11802814;
bios.MEM.instance("STACK").len = 0x00003000;
bios.MEM.instance("STACK").space = "code/data";
bios.MEM.STACKSEG = prog.get("STACK");
bios.MEM.GBLINITSEG = prog.get("SDRAM");
bios.MEM.BIOSSEG = prog.get("SDRAM");
bios.MEM.SYSINITSEG = prog.get("SDRAM");
bios.MEM.HWISEG = prog.get("SDRAM");
bios.MEM.HWIVECSEG = prog.get("SDRAM");
bios.MEM.RTDXTEXTSEG = prog.get("SDRAM");
bios.MEM.FARSEG = prog.get("SDRAM");
bios.MEM.TEXTSEG = prog.get("SDRAM");
bios.MEM.SWITCHSEG = prog.get("SDRAM");
bios.MEM.PINITSEG = prog.get("SDRAM");
bios.MEM.CONSTSEG = prog.get("SDRAM");
bios.MEM.DATASEG = prog.get("SDRAM");
bios.MEM.CIOSEG = prog.get("SDRAM");
bios.MEM.TEXTSEG = prog.get("IRAM");
bios.MEM.TEXTSEG = prog.get("L3_CBA_RAM");
bios.MEM.TEXTSEG = prog.get("IRAM");
bios.MEM.TEXTSEG = prog.get("SDRAM");
bios.MEM.TEXTSEG = prog.get("SDRAM");
bios.MEM.instance("SDRAM").base = 0xc0000060;
bios.MEM.instance("SDRAM").len = 0x00ffffa0;
bios.MEM.instance("IRAM").base = 0x11805814;
bios.MEM.instance("IRAM").len = 0x0003a7ec;
bios.MEM.instance("IRAM_DATA").destroy();
bios.MEM.create("SDRAM_C_int00_Call");
bios.MEM.instance("SDRAM_C_int00_Call").base = 0xc0000000;
bios.MEM.instance("SDRAM_C_int00_Call").len = 0x00000060;
bios.MEM.instance("SDRAM_C_int00_Call").space = "code/data";
bios.MEM.create("SDRAM_Data_Sec");
bios.MEM.instance("SDRAM_Data_Sec").base = 0xc0800000;
bios.MEM.instance("SDRAM_Data_Sec").len = 0x00800000;
bios.MEM.instance("SDRAM").len = 0x007fffa0;
bios.MEM.instance("Cint00_Call_Sec").destroy();
bios.MEM.NOMEMORYHEAPS = 0;
bios.MEM.instance("L3_CBA_RAM").createHeap = 1;
bios.MEM.instance("L3_CBA_RAM").heapSize = 0x00000800;
bios.MEM.BIOSOBJSEG = prog.get("L3_CBA_RAM");
bios.MEM.MALLOCSEG = prog.get("L3_CBA_RAM");
bios.UDEV.instance("UART0").initFxn = prog.extern("user_uart2_init");
bios.UDEV.instance("UART0").params = prog.extern("uart2Params");
bios.UDEV.instance("UART0").destroy();
bios.UDEV.create("UART2");
bios.UDEV.instance("UART2").fxnTableType = "IOM_Fxns";
bios.UDEV.instance("UART2").params = prog.extern("uart2Params");
bios.UDEV.instance("UART2").fxnTable = prog.extern("Uart_IOMFXNS");
bios.UDEV.instance("UART2").deviceId = 2;
bios.UDEV.instance("UART2").initFxn = prog.extern("user_uart2_init");
bios.UDEV.create("UART0");
bios.UDEV.create("UART1");
bios.UDEV.instance("UART0").initFxn = prog.extern("user_uart0_init");
bios.UDEV.instance("UART1").initFxn = prog.extern("user_uart1_init");
bios.UDEV.instance("UART0").fxnTable = prog.extern("Uart_IOMFXNS");
bios.UDEV.instance("UART1").fxnTable = prog.extern("Uart_IOMFXNS");
bios.UDEV.instance("UART0").params = prog.extern("uart2Params");
bios.UDEV.instance("UART0").fxnTableType = "IOM_Fxns";
bios.UDEV.instance("UART1").params = prog.extern("uart1Params");
bios.UDEV.instance("UART1").deviceId = 1;
bios.UDEV.instance("UART1").fxnTableType = "IOM_Fxns";
bios.UDEV.instance("UART0").params = prog.extern("uart0Params");
bios.SEM.create("Nav_Enable_Tsk_Sem");
bios.TSK.instance("TSK_idle").order = 1;
bios.TSK.instance("echoTask").order = 2;
bios.TSK.create("Nav_TSK");
bios.TSK.instance("Nav_TSK").order = 4;
bios.TSK.instance("Nav_TSK").fxn = prog.extern("NAV_Tsk");
bios.TSK.instance("Nav_TSK").priority = 9;
bios.TSK.instance("Nav_TSK").comment = "NAV_TSK";
bios.TSK.instance("Nav_TSK").fxn = prog.extern("Nav_Tsk");
bios.SEM.OBJMEMSEG = prog.get("SDRAM_Data_Sec");
bios.TSK.instance("Nav_TSK").stackSize = 6000;
bios.SEM.create("SEM0");
bios.SWI.create("Swi_Input_Debug_UART");
bios.SWI.instance("Swi_Input_Debug_UART").order = 1;
bios.SWI.create("Swi_Input_GPS_UART");
bios.SWI.instance("Swi_Input_GPS_UART").order = 2;
bios.SWI.create("Swi_Input_Host_UART");
bios.SWI.instance("Swi_Input_Host_UART").order = 3;
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.instance("echoTask").stackSize = 6000;
bios.TSK.instance("echoTask").priority = 15;
bios.TSK.instance("echoTask").allocateTaskName = 1;
bios.SEM.instance("SEM0").destroy();
bios.TSK.instance("echoTask").stackSize = 1000;
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").priority = 1;
bios.TSK.instance("echoTask").allocateTaskName = 0;
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.instance("echoTask").stackSize = 6000;
bios.TSK.instance("echoTask").priority = 15;
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.MEM.ARGSSEG = prog.get("IRAM");
bios.MEM.TRCDATASEG = prog.get("IRAM");
bios.MEM.SYSDATASEG = prog.get("IRAM");
bios.MEM.OBJSEG = prog.get("IRAM");
bios.MEM.FARSEG = prog.get("SDRAM_Data_Sec");
bios.MEM.CINITSEG = prog.get("SDRAM");
bios.MEM.CIOSEG = prog.get("IRAM");
bios.MEM.TRCDATASEG = prog.get("SDRAM");
bios.MEM.SYSDATASEG = prog.get("SDRAM");
bios.MEM.OBJSEG = prog.get("SDRAM");
bios.MEM.SWITCHSEG = prog.get("IRAM");
bios.MEM.FARSEG = prog.get("IRAM");
bios.MEM.CINITSEG = prog.get("IRAM");
bios.MEM.PINITSEG = prog.get("IRAM");
bios.MEM.CONSTSEG = prog.get("IRAM");
bios.MEM.DATASEG = prog.get("IRAM");
bios.MEM.FARSEG = prog.get("L3_CBA_RAM");
bios.MEM.FARSEG = prog.get("SDRAM");
bios.MEM.TRCDATASEG = prog.get("IRAM");
bios.MEM.SYSDATASEG = prog.get("IRAM");
bios.MEM.OBJSEG = prog.get("IRAM");
bios.MEM.SWITCHSEG = prog.get("SDRAM");
bios.MEM.FARSEG = prog.get("SDRAM_Data_Sec");
bios.MEM.CINITSEG = prog.get("SDRAM");
bios.MEM.PINITSEG = prog.get("SDRAM");
bios.MEM.CONSTSEG = prog.get("SDRAM");
bios.MEM.DATASEG = prog.get("SDRAM");
bios.MEM.instance("FLASH").len = 0x007fffff;
bios.MEM.instance("Boot_Asm_Sec").space = "code";
bios.MEM.instance("Boot_C_Next_Sec").space = "code";
bios.MEM.instance("Boot_C_Sec").space = "code";
bios.MEM.instance("Boot_Sig_Sec").space = "code";
bios.MEM.instance("SDRAM_Data_Sec").space = "code/data";
bios.LOG.instance("trace").destroy();
bios.LOG.create("LogTrace");
bios.LOG.instance("LogTrace").bufLen = 4096;
bios.MEM.BSSSEG = prog.get("SDRAM_Data_Sec");
bios.MEM.DATASEG = prog.get("SDRAM_Data_Sec");
bios.MEM.CIOSEG = prog.get("SDRAM_Data_Sec");
bios.MEM.TEXTSEG = prog.get("SDRAM_Data_Sec");
bios.MEM.TEXTSEG = prog.get("SDRAM");
bios.MEM.CINITSEG = prog.get("IRAM");
bios.MEM.SWITCHSEG = prog.get("IRAM");
bios.MEM.PINITSEG = prog.get("SDRAM_Data_Sec");
bios.MEM.CONSTSEG = prog.get("SDRAM_Data_Sec");
bios.MEM.GBLINITSEG = prog.get("IRAM");
bios.MEM.GBLINITSEG = prog.get("SDRAM");
bios.MEM.SWITCHSEG = prog.get("SDRAM");
bios.MEM.CINITSEG = prog.get("SDRAM");
bios.MEM.TRCDATASEG = prog.get("SDRAM");
bios.MEM.CONSTSEG = prog.get("SDRAM");
bios.MEM.TRCDATASEG = prog.get("IRAM");
bios.MEM.BSSSEG = prog.get("IRAM");
bios.MEM.PINITSEG = prog.get("SDRAM");
bios.MEM.DATASEG = prog.get("SDRAM");
bios.MEM.CIOSEG = prog.get("IRAM");
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Task");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.GIO.ENABLEGIO = 1;
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.create("COM");
bios.TSK.instance("COM").order = 5;
bios.TSK.instance("COM").comment = "Communication Task";
bios.SEM.create("ComSem");
bios.SEM.instance("ComSem").count = 1;
bios.SEM.instance("ComSem").comment = "Com Sync";
bios.TSK.instance("COM").fxn = prog.extern("COM_F_MainTask");
bios.TSK.instance("COM").priority = 15;
bios.TSK.instance("echoTask").priority = 14;
bios.SEM.instance("ComSem").count = 0;
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.instance("Nav_TSK").order = 2;
bios.TSK.instance("COM").order = 3;
bios.TSK.instance("echoTask").destroy();
bios.TSK.create("echoTask");
bios.TSK.instance("echoTask").arg3 = 0;
bios.TSK.instance("echoTask").autoAllocateStack = 1;
bios.TSK.instance("echoTask").arg2 = 0;
bios.TSK.instance("echoTask").arg7 = 0;
bios.TSK.instance("echoTask").filtmaxmult = 1;
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.instance("echoTask").arg6 = 0;
bios.TSK.instance("echoTask").arg1 = 0;
bios.TSK.instance("echoTask").envPointer = 0;
bios.TSK.instance("echoTask").avgformat = "%.2f inst";
bios.TSK.instance("echoTask").priority = 14;
bios.TSK.instance("echoTask").maxformat = "%g inst";
bios.TSK.instance("echoTask").iId = 0;
bios.TSK.instance("echoTask").arg0 = 0;
bios.TSK.instance("echoTask").arg5 = 0;
bios.TSK.instance("echoTask").filter = 2;
bios.TSK.instance("echoTask").exitFlag = 1;
bios.TSK.instance("echoTask").order = 2;
bios.TSK.instance("echoTask").sumformat = "%g inst";
bios.TSK.instance("echoTask").arg4 = 0;
bios.TSK.instance("echoTask").stackMemSeg = prog.get("IRAM");
bios.TSK.instance("echoTask").unittype = 0;
bios.TSK.instance("echoTask").comment = "Sample Application";
bios.TSK.instance("echoTask").allocateTaskName = 0;
bios.TSK.instance("echoTask").stackSize = 6000;
bios.TSK.instance("echoTask").iSTATREG = 0x00000000;
bios.TSK.instance("echoTask").filtsummult = 1;
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("COM").destroy();
bios.TSK.instance("echoTask").priority = 15;
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.create("Com_TSK");
bios.TSK.instance("Com_TSK").order = 4;
bios.TSK.instance("Com_TSK").priority = 15;
bios.TSK.instance("Com_TSK").stackSize = 6000;
bios.TSK.instance("Com_TSK").fxn = prog.extern("COM_F_MainTask");
bios.TSK.instance("echoTask").priority = 14;
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.HWI.instance("HWI_INT13").fxn = prog.extern("BSW_F_IrqHandle", "asm");
bios.HWI.instance("HWI_INT13").monitor = "Data Value";
bios.HWI.instance("HWI_INT13").fxn = prog.extern("BSW_F_IrqHandle");
bios.HWI.instance("HWI_INT13").monitor = "Nothing";
bios.HWI.instance("HWI_INT13").useDispatcher = 1;
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").order = 3;
bios.TSK.instance("Com_TSK").destroy();
bios.HWI.instance("HWI_INT13").interruptMask = "all";
bios.ECM.instance("EVENT52").fxn = prog.extern("BSW_F_IrqHandle");
bios.ECM.instance("EVENT63").fxn = prog.extern("BSW_F_IrqHandle");
bios.HWI.instance("HWI_INT13").fxn = prog.extern("ECM_dispatcher");
bios.HWI.instance("HWI_INT13").fxn = prog.extern("ECM_dispatch");
bios.HWI.instance("HWI_INT13").interruptMask = "self";
bios.ECM.instance("EVENT52").fxn = prog.extern("UTL_halt");
bios.ECM.instance("EVENT52").fxn = prog.extern("BSW_F_IrqHandle");
bios.ECM.instance("EVENT52").unmask = 0;
bios.HWI.instance("HWI_INT9").monitor = "Nothing";
bios.HWI.instance("HWI_INT9").fxn = prog.extern("BSW_F_IrqHandle");
bios.ECM.instance("EVENT52").fxn = prog.extern("UTL_halt");
bios.HWI.instance("HWI_INT13").interruptMask = "bitmask";
bios.ECM.instance("EVENT52").unmask = 1;
bios.HWI.instance("HWI_INT13").fxn = prog.extern("BSW_F_IrqHandle");
bios.HWI.instance("HWI_INT13").interruptMask = "self";
bios.ECM.instance("EVENT52").fxn = prog.extern("BSW_F_IrqHandle");
bios.HWI.instance("HWI_INT4").fxn = prog.extern("BSW_F_IrqHandle");
bios.HWI.instance("HWI_INT14").fxn = prog.extern("BSW_F_IrqHandle");
bios.HWI.instance("HWI_INT4").fxn = prog.extern("HWI_unused");
bios.HWI.instance("HWI_INT4").fxn = prog.extern("HWI_unused", "asm");
bios.HWI.instance("HWI_INT9").fxn = prog.extern("ECM_dispatch");
bios.HWI.instance("HWI_INT13").fxn = prog.extern("HWI_unused", "asm");
bios.HWI.instance("HWI_INT13").useDispatcher = 0;
bios.HWI.instance("HWI_INT14").fxn = prog.extern("HWI_unused", "asm");
bios.ECM.instance("EVENT52").fxn = prog.extern("UTL_halt");
bios.HWI.instance("HWI_INT13").fxn = prog.extern("BSW_F_IrqHandle");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.HWI.instance("HWI_INT4").fxn = prog.extern("intr13_SNAV");
bios.TSK.instance("echoTask").stackMemSeg = prog.get("SDRAM");
bios.TSK.instance("echoTask").priority = 15;
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.instance("echoTask").stackMemSeg = prog.get("IRAM");
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.create("Com_TSK");
bios.TSK.instance("Com_TSK").order = 4;
bios.TSK.instance("Com_TSK").stackSize = 6000;
bios.TSK.instance("Com_TSK").priority = 15;
bios.TSK.instance("Com_TSK").fxn = prog.extern("COM_F_MainTask");
bios.TSK.instance("echoTask").priority = 14;
bios.TSK.instance("echoTask").priority = 15;
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.instance("Com_TSK").priority = 14;
bios.SEM.instance("ComSem").count = 1;
bios.TSK.instance("Com_TSK").destroy();
bios.SEM.instance("ComSem").count = 0;
bios.SEM.create("COM_RxSem");
bios.SEM.instance("ComSem").destroy();
bios.SEM.create("COM_TxSem");
bios.SEM.instance("COM_TxSem").comment = "Com Sync";
bios.TSK.create("Com_RxTSK");
bios.TSK.instance("Com_RxTSK").order = 6;
bios.TSK.create("Com_TxTSK");
bios.TSK.instance("Com_TxTSK").order = 7;
bios.TSK.instance("Com_RxTSK").order = 4;
bios.TSK.instance("Com_TxTSK").order = 5;
bios.TSK.instance("Com_RxTSK").fxn = prog.extern("COM_F_RxMainTask");
bios.TSK.instance("Com_TxTSK").fxn = prog.extern("COM_F_TxMainCycle");
bios.TSK.instance("Com_TxTSK").priority = 14;
bios.TSK.instance("Com_RxTSK").priority = 14;
bios.TSK.instance("Com_TxTSK").stackSize = 6000;
bios.TSK.instance("Com_RxTSK").stackSize = 6000;
bios.TSK.instance("Com_RxTSK").stackMemSeg = prog.get("SDRAM");
bios.TSK.instance("Com_TxTSK").stackMemSeg = prog.get("SDRAM");
bios.TSK.instance("Com_RxTSK").priority = 15;
bios.TSK.instance("Com_TxTSK").priority = 15;
bios.TSK.instance("echoTask").priority = 14;
bios.TSK.instance("echoTask").priority = 15;
bios.TSK.instance("Com_TxTSK").stackMemSeg = prog.get("IRAM");
bios.TSK.instance("Com_TxTSK").stackSize = 3000;
bios.TSK.instance("Com_RxTSK").stackSize = 3000;
bios.TSK.instance("Com_RxTSK").stackMemSeg = prog.get("IRAM");
bios.TSK.instance("Com_RxTSK").priority = 14;
bios.TSK.instance("Com_TxTSK").priority = 14;
bios.SEM.create("COM_hEdmaProtect");
bios.SEM.instance("COM_hEdmaProtect").count = 1;
bios.SEM.instance("COM_hEdmaProtect").count = 0;
bios.TSK.instance("Com_RxTSK").priority = 15;
bios.TSK.instance("Com_TxTSK").priority = 15;
bios.TSK.instance("echoTask").priority = 13;
bios.TSK.instance("Com_RxTSK").priority = 14;
bios.TSK.instance("Com_TxTSK").priority = 14;
bios.TSK.instance("echoTask").priority = 15;
bios.TSK.instance("Com_RxTSK").priority = 13;
bios.TSK.instance("Com_RxTSK").stackSize = 6000;
bios.TSK.instance("Com_TxTSK").stackSize = 6000;
bios.TSK.instance("Com_RxTSK").stackMemSeg = prog.get("SDRAM");
bios.TSK.instance("Com_TxTSK").stackMemSeg = prog.get("SDRAM");
bios.TSK.instance("Com_RxTSK").priority = 14;
bios.MEM.instance("L3_CBA_RAM").heapSize = 0x00003000;
bios.MEM.instance("L3_CBA_RAM").heapSize = 0x00006000;
bios.TSK.instance("Com_TxTSK").priority = 13;
bios.TSK.instance("Com_TxTSK").priority = 14;
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.instance("echoTask").priority = 14;
bios.TSK.instance("Com_TxTSK").priority = 15;
bios.TSK.instance("Com_RxTSK").priority = 15;
bios.TSK.instance("Com_RxTSK").stackMemSeg = prog.get("IRAM");
bios.TSK.instance("Com_TxTSK").stackMemSeg = prog.get("IRAM");
bios.TSK.instance("echoTask").priority = 13;
bios.TSK.instance("Com_TxTSK").priority = 14;
bios.TSK.instance("Com_TxTSK").priority = 15;
bios.TSK.instance("Com_TxTSK").priority = 14;
bios.TSK.instance("Com_RxTSK").priority = 14;
bios.TSK.instance("Com_TxTSK").priority = 15;
bios.TSK.instance("echoTask").priority = 15;
bios.TSK.instance("Com_TxTSK").priority = 14;
bios.TSK.instance("echoTask").priority = 13;
bios.TSK.instance("Com_RxTSK").priority = 15;
bios.TSK.instance("Com_TxTSK").priority = 15;
bios.TSK.instance("Com_TxTSK").priority = 14;
bios.HWI.instance("HWI_INT4").interruptSelectNumber = 52;
bios.HWI.instance("HWI_INT4").interruptSelectNumber = 4;
bios.SEM.instance("COM_hEdmaProtect").destroy();
bios.SEM.create("SEM_Nothing");
bios.TSK.create("NothingTask");
bios.TSK.instance("NothingTask").order = 6;
bios.TSK.instance("NothingTask").fxn = prog.extern("MNG_F_Nothing");
bios.TSK.instance("NothingTask").fxn = prog.extern("NAV_F_Nothing");
bios.TSK.instance("Com_RxTSK").stackSize = 2048;
bios.TSK.instance("Com_TxTSK").stackSize = 2048;
bios.TSK.instance("Com_RxTSK").stackSize = 6000;
bios.TSK.instance("Com_TxTSK").stackSize = 6000;
bios.TSK.instance("Com_RxTSK").stackSize = 2048;
bios.TSK.instance("Com_TxTSK").stackSize = 2048;
bios.SEM.instance("SEM_Nothing").destroy();
bios.TSK.instance("NothingTask").destroy();
bios.GBL.C64PLUSCONFIGURE = 0;
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.HWI.instance("HWI_INT13").interruptSelectNumber = 52;
bios.HWI.instance("HWI_INT13").useDispatcher = 1;
bios.HWI.instance("HWI_INT13").interruptMask = "all";
bios.ECM.instance("EVENT63").fxn = prog.extern("UTL_halt");
bios.HWI.instance("HWI_INT13").interruptMask = "none";
bios.HWI.instance("HWI_INT13").fxn = prog.extern("HWI_unused", "asm");
bios.HWI.instance("HWI_INT13").fxn = prog.extern("BSW_F_IrqHandle");
bios.ECM.instance("EVENT52").unmask = 0;
bios.HWI.RESETVECTOR = 0;
bios.HWI.ENABLEEXC = 0;
bios.HWI.instance("HWI_INT13").monitor = "Data Value";
bios.HWI.instance("HWI_INT13").monitor = "Nothing";
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.ECM.ENABLE = 0;
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.ECM.ENABLE = 1;
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.ECM.ENABLE = 0;
bios.ECM.ENABLE = 1;
bios.HWI.instance("HWI_INT13").monitor = "Nothing";
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.HWI.instance("HWI_INT13").useDispatcher = 0;
bios.HWI.instance("HWI_INT13").useDispatcher = 1;
bios.HWI.instance("HWI_INT13").fxn = prog.extern("HWI_unused", "asm");
bios.HWI.instance("HWI_INT13").interruptSelectNumber = 11;
bios.HWI.instance("HWI_INT6").fxn = prog.extern("BSW_F_IrqHandle");
bios.HWI.instance("HWI_INT6").interruptSelectNumber = 52;
bios.HWI.instance("HWI_INT6").useDispatcher = 1;
bios.HWI.instance("HWI_INT6").fxn = prog.extern("ECM_dispatch");
bios.HWI.instance("HWI_INT6").interruptSelectNumber = 1;
bios.HWI.instance("HWI_INT6").interruptSelectNumber = 6;
bios.ECM.instance("EVENT52").fxn = prog.extern("BSW_F_IrqHandle");
bios.ECM.instance("EVENT52").unmask = 1;
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.ECM.instance("EVENT52").unmask = 0;
bios.HWI.instance("HWI_INT4").fxn = prog.extern("BSW_F_IrqHandle");
bios.HWI.instance("HWI_INT4").interruptSelectNumber = 52;
bios.HWI.instance("HWI_INT4").useDispatcher = 1;
bios.HWI.instance("HWI_INT4").interruptMask = "all";
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Task");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.HWI.instance("HWI_INT4").fxn = prog.extern("HNS_F_PBIrqHendler");
bios.HWI.instance("HWI_INT5").fxn = prog.extern("intr13_SNAV");
bios.HWI.instance("HWI_INT5").useDispatcher = 1;
bios.HWI.instance("HWI_INT5").interruptSelectNumber = 54;
bios.HWI.instance("HWI_INT5").interruptMask = "all";
bios.SEM.create("SEM0");
bios.HWI.instance("HWI_INT5").fxn = prog.extern("MNG_F_RTCIrqHandle");
bios.HWI.instance("HWI_INT5").fxn = prog.extern("intr13_SNAV");
bios.HWI.instance("HWI_INT5").fxn = prog.extern("MNG_F_RTCIrqHandle");
bios.ECM.instance("EVENT52").fxn = prog.extern("UTL_halt");
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.HWI.instance("HWI_INT6").fxn = prog.extern("MNG_F_ShutDownIrqHndle");
bios.HWI.instance("HWI_INT6").useDispatcher = 1;
bios.HWI.instance("HWI_INT6").interruptSelectNumber = 49;
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("Com_TxTSK").priority = -1;
bios.TSK.instance("Com_RxTSK").priority = -1;
bios.HWI.instance("HWI_INT14").interruptSelectNumber = 69;
bios.HWI.instance("HWI_INT14").useDispatcher = 1;
bios.HWI.instance("HWI_INT14").interruptMask = "all";
bios.HWI.instance("HWI_INT14").fxn = prog.extern("UART_F_Uart2IrqHandle");
bios.TSK.instance("Com_TxTSK").order = 4;
bios.TSK.instance("Com_RxTSK").destroy();
bios.TSK.instance("Com_TxTSK").destroy();
bios.UDEV.instance("UART0").initFxn = prog.extern("UART_F_InitChannel0");
bios.UDEV.instance("UART0").params = prog.extern("UART_t_Uart0Params");
bios.UDEV.instance("UART1").params = prog.extern("UART_t_Uart1Params");
bios.UDEV.instance("UART1").initFxn = prog.extern("UART_F_InitChannel1");
bios.UDEV.instance("UART2").initFxn = prog.extern("UART_F_InitChannel2");
bios.UDEV.instance("UART2").params = prog.extern("UART_t_Uart2Params");
bios.HWI.instance("HWI_INT14").arg = 2;
bios.HWI.instance("HWI_INT14").fxn = prog.extern("UART_F_UartIrqHandle");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.SEM.instance("COM_RxSem").destroy();
bios.SEM.instance("COM_TxSem").destroy();
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.HWI.instance("HWI_INT14").interruptMask = "self";
bios.TSK.create("TxTSK");
bios.TSK.instance("TxTSK").order = 4;
bios.TSK.instance("TxTSK").fxn = prog.extern("UART_F_TxTsk");
bios.TSK.instance("TxTSK").stackSize = 2048;
bios.TSK.instance("TxTSK").priority = 15;
bios.HWI.instance("HWI_INT14").monitor = "Stack Pointer";
bios.SWI.instance("PRD_swi").order = 1;
bios.SWI.instance("KNL_swi").order = 2;
bios.SWI.instance("Swi_Input_GPS_UART").order = 3;
bios.SWI.instance("Swi_Input_Host_UART").order = 4;
bios.SWI.instance("Swi_Input_Debug_UART").destroy();
bios.SWI.instance("Swi_Input_Host_UART").order = 3;
bios.SWI.instance("Swi_Input_GPS_UART").destroy();
bios.SWI.instance("Swi_Input_Host_UART").destroy();
bios.SWI.create("Swi_UartRx");
bios.SWI.instance("Swi_UartRx").order = 4;
bios.SWI.instance("Swi_UartRx").fxn = prog.extern("UART_F_SwiUartRxHandler");
bios.TSK.instance("TxTSK").stackSize = 1024;
bios.TSK.instance("echoTask").stackSize = 8000;
bios.UDEV.instance("UART0").destroy();
bios.UDEV.instance("UART1").destroy();
bios.UDEV.instance("UART2").destroy();
bios.TSK.instance("echoTask").stackSize = 6000;
bios.TSK.instance("echoTask").stackSize = 8000;
bios.HWI.instance("HWI_INT14").interruptSelectNumber = 38;
bios.HWI.instance("HWI_INT14").interruptSelectNumber = 69;
bios.TSK.instance("TxTSK").destroy();
bios.HWI.instance("HWI_INT14").interruptSelectNumber = 38;
bios.HWI.instance("HWI_INT14").interruptSelectNumber = 69;
bios.TSK.create("COM_TxTsk");
bios.TSK.instance("COM_TxTsk").order = 4;
bios.TSK.instance("COM_TxTsk").fxn = prog.extern("UART_F_TxTsk");
bios.TSK.instance("COM_TxTsk").stackSize = 2048;
bios.TSK.instance("COM_TxTsk").priority = 14;
bios.HWI.instance("HWI_INT4").fxn = prog.extern("UART_F_UartIrqHandle");
bios.HWI.instance("HWI_INT4").interruptSelectNumber = 69;
bios.HWI.instance("HWI_INT14").interruptSelectNumber = 52;
bios.HWI.instance("HWI_INT14").fxn = prog.extern("HNS_F_PBIrqHendler");
bios.HWI.instance("HWI_INT14").monitor = "Nothing";
bios.HWI.instance("HWI_INT14").interruptMask = "all";
bios.HWI.instance("HWI_INT14").arg = 0;
bios.HWI.instance("HWI_INT4").arg = 2;
bios.TSK.create("COM_RxTsk");
bios.TSK.instance("COM_RxTsk").order = 5;
bios.TSK.instance("COM_RxTsk").priority = 15;
bios.TSK.instance("COM_RxTsk").stackSize = 2048;
bios.TSK.instance("COM_RxTsk").fxn = prog.extern("UART_F_RxTsk");
bios.HWI.instance("HWI_INT4").interruptSelectNumber = 38;
bios.TSK.instance("COM_RxTsk").priority = -1;
bios.HWI.instance("HWI_INT4").interruptMask = "bitmask";
bios.HWI.instance("HWI_INT4").interruptBitMask = 0xfff7;
bios.HWI.instance("HWI_INT4").interruptSelectNumber = 69;
bios.HWI.instance("HWI_INT4").interruptMask = "none";
bios.HWI.instance("HWI_INT4").interruptMask = "self";
bios.HWI.instance("HWI_INT4").interruptMask = "bitmask";
bios.HWI.instance("HWI_INT4").interruptBitMask = 0xffef;
bios.SEM.create("SEM_Tx");
bios.TSK.instance("echoTask").fxn = prog.extern("echo");
bios.TSK.instance("echoTask").fxn = prog.extern("MNG_Task");
bios.TSK.instance("echoTask").fxn = prog.extern("Manager_Tsk");
bios.HWI.instance("HWI_INT5").fxn = prog.extern("HWI_unused", "asm");
bios.MEM.STACKSIZE = 0x1000;
bios.HWI.instance("HWI_INT5").fxn = prog.extern("MNG_F_RTCIrqHandle");
bios.TSK.instance("COM_RxTsk").destroy();
bios.HWI.instance("HWI_INT4").fxn = prog.extern("UART_F_Uart2IrqHandle");
bios.HWI.instance("HWI_INT13").fxn = prog.extern("MNG_F_RTCIrqHandle");
bios.HWI.instance("HWI_INT13").interruptSelectNumber = 54;
bios.HWI.instance("HWI_INT13").useDispatcher = 1;
bios.HWI.instance("HWI_INT13").interruptMask = "all";
bios.HWI.instance("HWI_INT5").interruptSelectNumber = 38;
bios.HWI.instance("HWI_INT5").fxn = prog.extern("UART_F_Uart0IrqHandle");
bios.HWI.instance("HWI_INT10").fxn = prog.extern("MNG_F_ShutDownIrqHndle");
bios.HWI.instance("HWI_INT10").interruptSelectNumber = 49;
bios.HWI.instance("HWI_INT6").fxn = prog.extern("HWI_unused", "asm");
bios.HWI.instance("HWI_INT6").interruptSelectNumber = 46;
bios.HWI.instance("HWI_INT6").fxn = prog.extern("UART_F_Uart1IrqHandle");
bios.SWI.create("Swi_Uart1Rx");
bios.SWI.instance("Swi_Uart1Rx").order = 5;
bios.SWI.create("Swi_Uart0Rx");
bios.SWI.instance("Swi_Uart0Rx").order = 6;
bios.SWI.instance("Swi_Uart1Rx").order = 3;
bios.SWI.instance("Swi_Uart0Rx").order = 4;
bios.SWI.instance("Swi_UartRx").destroy();
bios.SWI.create("Swi_Uart2Rx");
bios.SWI.instance("Swi_Uart2Rx").order = 6;
bios.SWI.instance("Swi_Uart2Rx").fxn = prog.extern("UART_F_SwiUartRxHandler");
bios.SWI.instance("Swi_Uart2Rx").fxn = prog.extern("UART_F_SwiUart2RxHandler");
bios.SWI.instance("Swi_Uart1Rx").fxn = prog.extern("UART_F_SwiUart1RxHandler");
bios.SWI.instance("Swi_Uart0Rx").fxn = prog.extern("UART_F_SwiUart0RxHandler");
bios.HWI.instance("HWI_INT4").interruptMask = "all";
bios.HWI.instance("HWI_INT6").interruptMask = "all";
bios.HWI.instance("HWI_INT6").arg = 1;
bios.SWI.instance("Swi_Uart1Rx").arg0 = 1;
bios.SWI.instance("Swi_Uart2Rx").arg0 = 2;
// !GRAPHICAL_CONFIG_TOOL_SCRIPT_INSERT_POINT!
prog.gen();

0 Mukul Bhatnagar over 15 years ago in reply to Yoav Gold

TI__Guru* 84325 points

Hi Yoav

Thanks for sharing the bios configuration file and clarifying the use of ECM etc. Unfortunately I have not been able to pin point on anything that could be causing the issue so far. It would be great if you also provide details on what other peripherals/interrupts can be happening in conjunction with the UART transfers and interrupts in your system. I was trying to deduce that from the .tcf file , but since in text format it seems to "append" to previously saved/configured settings, it is hard for me to completely decipher the last setting with your final interrupt mapping.

Additionally, I am out of office for the next 2 weeks, so I am hoping someone else from the community/TI would continue helping you in resolving this issue. Since the email trail on this has increased quite a bit, I will try to summarize the issue/ debug steps undertaken so far. Please feel free to correct and add any relevant details to this summary.

------

CPU Speed 300 MHz, UART baud rate: 115200 bps, UART transfers serviced by CPU

Custom UART driver implementation (not using PSP drivers)

Using CC3.3, Bios 5.41.01.09, C.G.T 6.1.12

Issue: RX only or Tx only scenarios work fine. However, if a high priority task is used to transmit data periodically, while receiving data from PC terminal, there is occassional "unidentified" UART interrupts, where the IIR status seems to be 0x0 and IPEND is 0x1 (no interrupts pending)

Debug Status
1) The issue happens only when UART Tx/Rx is done using 2 terminals connected to each other. With internal loop back or external loopback or half duplex scenarios there are no issues observed
2) The issue can be reproduced using UART2 or UART0. Have also tried swapping PC, terminal, connector, etc
3) Reducing the baudrate did not seem to reduce/eliminate the random failures
4) The behavior can be reproduced both with tranmits done using UART TX interrupt or just polling & tranmitting
5) The current test case has RX threshold set to 1 byte, increasing the threshold seems to increase the failure rate.
6) UART interrupt is directly mapped to an HWI (HWI 4), the ECM is not used
7) No other interrupts in the system(?)
8) Initially the HWI handler invoked a SWI that would have the handling function, reading the IIR value etc. Directly having the IIR status read and handling in the HWI handler (eliminating invoking a SWI) does not eliminate the failure
9) DMAMODE is disabled. Enabling/Disabling this bit does not impact the failure
10) Originally EDSSI bit was being enabled, a modem status interrupt has an IIR ID of 0x0 , but disabling this did not eliminate the occurence of unidentified UART interrupts

0 Yoav Gold over 15 years ago in reply to Mukul Bhatnagar

Prodigy 250 points

This summs it up ok,
The problem hasnt been solved yet, I really hope someon will pick it up where you left it,

In the meantime, Thanks for all your help.

Yoav.

0 Brad Griffis over 15 years ago in reply to Yoav Gold

TI__Guru*** 125430 points

The behavior you describe sounds like the type of thing you would see when a framing error occurs. In this case should get a "line status" interrupt. You would need to clear the interrupt by reading the erroneous data from RBR. My experience on other devices has been that the data reads back as 0x00 in that case, just as you are seeing.

Your ISR code does not look to handle this specific condition and so I wonder if that's why you are getting the interrupt with "nothing". In terms of solving the framing error, this can generally be fixed by inserting a little bit more space between characters. For example, in Tera Term, there is an option in the serial port setup to configure the delay between characters. Please try putting a tiny bit of delay in there (e.g. 1ms in Tera Term). I think 100 microseconds would probably be plenty, maybe even 50 microseconds. I'm not sure if fractional delays are allowed in Tera Term, though if you have a processor on the other end that's probably a little easier.

Brad

0 Yoav Gold over 15 years ago in reply to Brad Griffis

Prodigy 250 points

Hi brad, Thanks for your replay

Ill try to measure the time between bytes I send to the DSP and insert a delay between them. Ill tell you how It went.
By the way, Can you see how it connects to the fact that this happens only when I'm transmitting and receiving together?

Is there some defined period of time needed as a minimum delay between bytes sent to/from the system?

but I 'm not sure this is the case.

1.I have another channel (UART 0 ) where I do get identified "Line Status" interrupts reporting me with Framing error. In that case, I go and clear the erroneous data from the RBR (It is added in a newer version of my code) but I also get these unidentified interrupts.

2.I held a test where I went and read the data from the RBR even when the interrupt was unuidentified and what I get was a byte previusly inserted into the fifo (something that loops with the 16 bytes fifo). this is an update from the previous post.

3.the Interrupt pending bit (IIR[0]) is '1' when these interrupts are received, does it still sound like a framing error?

Anyway, thanks, Ill look into the delay thing

If you have any more ideas, I would really appreciate it.

Yoav

0 Brad Griffis over 15 years ago in reply to Yoav Gold

TI__Guru*** 125430 points

Please post your updated ISR code. Let us know how the test goes with adding delay between transmitted data.

0 Yoav Gold over 15 years ago in reply to Brad Griffis

Prodigy 250 points

hi brad,

Below are the files. Ill keep you updated on the experiment.

the function that does most of the work is UART_F_UartRxHandler()

it is called from the HWI handler : UART_F_Uart"n"IrqHandle which is written in the tcf file as the ISR.

ask me if something isnt clear here

Thanks,

Yoav

UART.C

/*
* NewUart.c
*
* Created on: 01/12/2009
*      Author: DP24288
*/

/******************************************* Includes *******************************************/
/* System includes */

#ifndef LDR_CSCI
    #include "RevCcfg.h"
#else
    #include "LDRRevCcfg.h"
#endif
#include <Uart.h>
#include "Psc.h"
#include "cslr.h"
#include "csl_types.h"
#include "cslr_uart.h"
#include <cslr_gpio.h>
#include <cslr_syscfg_C6747.h>
#include <soc_C6747.h>
#include <hwi.h>
#include <c64.h>
#include <tsk.h>

/*   SW includes   */
#include "NewUart.h"

/******************************************* Externals *******************************************/
extern CSL_SyscfgRegsOvly        BSW_t_SysRegs;
extern CSL_GpioBankRegsOvly    BSW_t_GpioBank23Regs;
/******************************************* Static and Globals   *******************************************/

static CSL_UartRegsOvly        BSW_t_Uart0Regs            = (CSL_UartRegsOvly)CSL_UART_0_REGS;
static CSL_UartRegsOvly        BSW_t_Uart1Regs            = (CSL_UartRegsOvly)CSL_UART_1_REGS;
static CSL_UartRegsOvly        BSW_t_Uart2Regs            = (CSL_UartRegsOvly)CSL_UART_2_REGS;

Uint8 UART_au8_RS232OutputBuffer[UART_BUFFERSIZE];
Uint8 UART_au8_RS232InputBuffer[UART_BUFFERSIZE];
Uint8 UART_au8_USBOutputBuffer[UART_BUFFERSIZE];
Uint8 UART_au8_USBInputBuffer[UART_BUFFERSIZE];
#ifndef LDR_CSCI
    Uint8 UART_au8_GPSOutputBuffer[UART_BUFFERSIZE];
    Uint8 UART_au8_GPSInputBuffer[UART_BUFFERSIZE];
#endif

/* Temporary Debug Globals */
Uint32 UART_u32_IrqCounter[NUM_OF_UARTS]        = {0,0,0};
Uint32 UART_u32_IrqProblemCounter[NUM_OF_UARTS] = {0,0,0};
Uint32 UART_u32_IrqRxCounterTO[NUM_OF_UARTS]    = {0,0,0};
Uint32 UART_u32_IrqRxCounterDR[NUM_OF_UARTS]    = {0,0,0};
Uint32 UART_u32_IrqTxCounter[NUM_OF_UARTS]      = {0,0,0};
Uint32 UART_u32_BytesReceived[NUM_OF_UARTS]     = {0,0,0};
Uint32 UART_u32_StillSending[NUM_OF_UARTS]      = {0,0,0};
Uint32 UART_u32_BytesSent[NUM_OF_UARTS]            = {0,0,0};
Uint32 UART_u32_DefaultCounter[NUM_OF_UARTS]    = {0,0,0};

#define UART_COMPONENT_FIFO_SIZE    16

/******************************************* Functions *******************************************/

/***************************************************************************
--$(S
1. CSU Name:                                     CSU#
2. CSU Purpose:
3. Input/Output Data Elements:
    Input data elements:
        N/A
    Output data elements:
        N/A
4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
    N/A
--$)S
***************************************************************************/
void UART_F_NewInit()
{
    UART_E_PortID e_PortID;
    CSL_UartRegsOvly pt_RegSet;

    UART_F_InitGlobals();

    /* enable transmitter and receiver (Reset and then enable) */
    for(e_PortID = USB_UART_ID; e_PortID < NUM_OF_UARTS; e_PortID++)
    {
        pt_RegSet = UART_at_ChannelDBTable[e_PortID].pt_RegSet;
        CSL_FINST(pt_RegSet->PWREMU_MGMT,UART_PWREMU_MGMT_UTRST,RESET);

        CSL_FINST(pt_RegSet->PWREMU_MGMT,UART_PWREMU_MGMT_URRST,RESET);
    }

    TSK_sleep(1);

    UART_F_InitSysRegs();
    UART_F_InitBaudRate();
    UART_F_InitFifo();
    UART_F_InitComProtocol();
    UART_F_DefineInterrupts();

    /* enable transmitter and receiver (Reset and then enable) */
    for(e_PortID = USB_UART_ID; e_PortID < NUM_OF_UARTS; e_PortID++)
    {
        pt_RegSet = UART_at_ChannelDBTable[e_PortID].pt_RegSet;
        CSL_FINST(pt_RegSet->PWREMU_MGMT,UART_PWREMU_MGMT_UTRST,ENABLE);
        CSL_FINST(pt_RegSet->PWREMU_MGMT,UART_PWREMU_MGMT_URRST,ENABLE);
    }

    return;
}
/***************************************************************************
--$(S
1. CSU Name: UART_F_InitChannelDBTable                         CSU#
2. CSU Purpose:
        Init the Channel DB table
3. Input/Output Data Elements:
    Input data elements:
        None
    Output data elements:
        None
4. Algorithm & Logic Flow:
        None
5. Error Handling & Limitations:
        None
--$)S
***************************************************************************/
void UART_F_InitGlobals()
{

    /* Init Global buffer */
    memset( UART_au8_RS232OutputBuffer        , 0, UART_BUFFERSIZE*sizeof(Uint8) );
    memset( UART_au8_USBOutputBuffer         , 0, UART_BUFFERSIZE*sizeof(Uint8) );
#ifndef LDR_CSCI
    memset( UART_au8_GPSOutputBuffer         , 0, UART_BUFFERSIZE*sizeof(Uint8) );
    memset( UART_au8_GPSInputBuffer            , 0, UART_BUFFERSIZE*sizeof(Uint8) );
#endif
    memset( UART_au8_RS232InputBuffer          , 0, UART_BUFFERSIZE*sizeof(Uint8) );
    memset( UART_au8_USBInputBuffer            , 0, UART_BUFFERSIZE*sizeof(Uint8) );

    UART_F_InitChannelDBTable();
    return;
}
/***************************************************************************
--$(S
1. CSU Name: UART_F_InitChannelDBTable                         CSU#
2. CSU Purpose:
        Init the Channel DB table
3. Input/Output Data Elements:
    Input data elements:
        None
    Output data elements:
        None
4. Algorithm & Logic Flow:
        None
5. Error Handling & Limitations:
        None
--$)S
***************************************************************************/
void   UART_F_InitChannelDBTable()
{
    /* Debugging GPS channel */
    /*
    Uint32 u32_index;
    for(u32_index = 0; u32_index < UART_BUFFERSIZE; u32_index++)
    {
        UART_au8_GPSInputBuffer[u32_index] = u32_index;
    }
    */
    /* End of Debugging GPS channel Block */

    /* Set Channel table */
    memset(UART_at_ChannelDBTable[GPS_UART_ID].Indexes[0] , 0, NUM_OF_FIFO_OPS*sizeof(Uint16) );
    memset(UART_at_ChannelDBTable[GPS_UART_ID].Indexes[1] , 0, NUM_OF_FIFO_OPS*sizeof(Uint16) );
#ifndef LDR_CSCI
    UART_at_ChannelDBTable[GPS_UART_ID].Buffer[FIFO_TX] = UART_au8_GPSOutputBuffer;
    UART_at_ChannelDBTable[GPS_UART_ID].Buffer[FIFO_RX] = UART_au8_GPSInputBuffer;
#endif
    UART_at_ChannelDBTable[GPS_UART_ID].u32_CycBuffersize = UART_BUFFERSIZE;
    UART_at_ChannelDBTable[GPS_UART_ID].pt_RegSet         = BSW_t_Uart1Regs;

    memset(UART_at_ChannelDBTable[USB_UART_ID].Indexes[0] , 0, NUM_OF_FIFO_OPS*sizeof(Uint16) );
    memset(UART_at_ChannelDBTable[USB_UART_ID].Indexes[1] , 0, NUM_OF_FIFO_OPS*sizeof(Uint16) );
    UART_at_ChannelDBTable[USB_UART_ID].Buffer[FIFO_TX] = UART_au8_USBOutputBuffer;
    UART_at_ChannelDBTable[USB_UART_ID].Buffer[FIFO_RX] = UART_au8_USBInputBuffer;
    UART_at_ChannelDBTable[USB_UART_ID].u32_CycBuffersize = UART_BUFFERSIZE;
    UART_at_ChannelDBTable[USB_UART_ID].pt_RegSet         = BSW_t_Uart0Regs;

    memset(UART_at_ChannelDBTable[RS232_UART_ID].Indexes[0], 0, NUM_OF_FIFO_OPS*sizeof(Uint16));
    memset(UART_at_ChannelDBTable[RS232_UART_ID].Indexes[1], 0, NUM_OF_FIFO_OPS*sizeof(Uint16));
    UART_at_ChannelDBTable[RS232_UART_ID].Buffer[FIFO_TX] = UART_au8_RS232OutputBuffer;
    UART_at_ChannelDBTable[RS232_UART_ID].Buffer[FIFO_RX] = UART_au8_RS232InputBuffer;
    UART_at_ChannelDBTable[RS232_UART_ID].u32_CycBuffersize = UART_BUFFERSIZE;
    UART_at_ChannelDBTable[RS232_UART_ID].pt_RegSet         = BSW_t_Uart2Regs;

    /* Debugging GPS channel */
    //UART_at_ChannelDBTable[GPS_UART_ID].Indexes[FIFO_TX][WRITE_INDEX] = UART_BUFFERSIZE;
    /* End of Debugging GPS channel Block */

    return;
}
/***************************************************************************
--$(S
1. CSU Name:                                     CSU#
2. CSU Purpose:
3. Input/Output Data Elements:
    Input data elements:
        N/A
    Output data elements:
        N/A
4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
    N/A
--$)S
***************************************************************************/
void UART_F_InitSysRegs()
{
    BSW_t_SysRegs->KICK0R = 0x83e70b13;
    BSW_t_SysRegs->KICK1R = 0x95A4F1E0;
    BSW_t_SysRegs->CFGCHIP0 = CSL_FMKT(SYSCFG_CFGCHIP0_PLL_MASTER_LOCK, FREE);

    /* For UART 0 */
    CSL_FINST(BSW_t_SysRegs->PINMUX8, SYSCFG_PINMUX8_PINMUX8_15_12, UART0_RXD);
    CSL_FINST(BSW_t_SysRegs->PINMUX8, SYSCFG_PINMUX8_PINMUX8_19_16, UART0_TXD);

    /* For UART 1 */
    CSL_FINST(BSW_t_SysRegs->PINMUX11, SYSCFG_PINMUX11_PINMUX11_11_8, UART1_RXD);
    CSL_FINST(BSW_t_SysRegs->PINMUX11, SYSCFG_PINMUX11_PINMUX11_15_12, UART1_TXD);

    /* For UART 2 */
    CSL_FINST(BSW_t_SysRegs->PINMUX8, SYSCFG_PINMUX8_PINMUX8_31_28, UART2_RXD);
    CSL_FINST(BSW_t_SysRegs->PINMUX9, SYSCFG_PINMUX9_PINMUX9_3_0, UART2_TXD);
}
/***************************************************************************
--$(S
1. CSU Name:                                     CSU#
2. CSU Purpose:
3. Input/Output Data Elements:
    Input data elements:
        N/A
    Output data elements:
        N/A
4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
    N/A
--$)S
***************************************************************************/
void UART_F_InitBaudRate()
{

    UART_E_PortID e_PortID;
    CSL_UartRegsOvly pt_RegSet;

    for(e_PortID = USB_UART_ID; e_PortID < NUM_OF_UARTS; e_PortID++)
    {
        pt_RegSet = UART_at_ChannelDBTable[e_PortID].pt_RegSet;

        /* Define the sampling rate
        * Using this sampling rate, you can define the baudrate according to this :
        * DIVISOR = "UART input clock" / Desired Baudrate*Sampling
        * */
        CSL_FINST(pt_RegSet->MDR, UART_MDR_OSM_SEL, 16XOVERSAMPLING);

        /* Allow access to the divisor latch */
        CSL_FINST(pt_RegSet->LCR, UART_LCR_DLAB, ENABLE);

        /* Set the divisor High and Low Bytes */
        CSL_FINS(pt_RegSet->DLH, UART_DLH_DLH, UART_DIVISOR_FOR_115200_x16SAMPLING >> 8);
        CSL_FINS(pt_RegSet->DLL, UART_DLL_DLL, UART_DIVISOR_FOR_115200_x16SAMPLING & 0x00FF);
/*
        if(e_PortID == GPS_UART_ID)
        {
            CSL_FINS(pt_RegSet->DLH, UART_DLH_DLH, UART_DIVISOR_FOR_9600_x13SAMPLING >> 8);
            CSL_FINS(pt_RegSet->DLL, UART_DLL_DLL, UART_DIVISOR_FOR_9600_x13SAMPLING & 0x00FF);
        }
        else
        {
            CSL_FINS(pt_RegSet->DLH, UART_DLH_DLH, UART_DIVISOR_FOR_115200_x13SAMPLING >> 8);
            CSL_FINS(pt_RegSet->DLL, UART_DLL_DLL, UART_DIVISOR_FOR_115200_x13SAMPLING & 0x00FF);
        }
*/

    }

    return;
}

/***************************************************************************
--$(S
1. CSU Name:                                     CSU#
2. CSU Purpose:
3. Input/Output Data Elements:
    Input data elements:
        N/A
    Output data elements:
        N/A
4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
    N/A
--$)S
***************************************************************************/
void UART_F_InitFifo()
{
    UART_E_PortID e_PortID;
    CSL_UartRegsOvly pt_RegSet;

    for(e_PortID = USB_UART_ID; e_PortID < NUM_OF_UARTS; e_PortID++)
    {
        pt_RegSet = UART_at_ChannelDBTable[e_PortID].pt_RegSet;
        /* Enable the Fifo */
        CSL_FINST(pt_RegSet->FCR, UART_FCR_FIFOEN, ENABLE);

        /* Clear Both fifos */
        CSL_FINST(pt_RegSet->FCR, UART_FCR_RXCLR, CLR);
        CSL_FINST(pt_RegSet->FCR, UART_FCR_TXCLR, CLR);

        /* Disable DMA */
        CSL_FINST(pt_RegSet->FCR, UART_FCR_DMAMODE1, DISABLE);
        /*    Receiver FIFO trigger level */
        /*
            RXFIFTL sets the trigger level for the receiver FIFO. When the trigger level
            is reached, a receiver data-ready interrupt is generated (if the interrupt request is enabled). Once the
            FIFO drops below the trigger level, the interrupt is cleared.
        */
        CSL_FINST(pt_RegSet->FCR, UART_FCR_RXFIFTL, CHAR1);
    }

    return;
}
/***************************************************************************
--$(S
1. CSU Name:                                     CSU#
2. CSU Purpose:
3. Input/Output Data Elements:
    Input data elements:
        N/A
    Output data elements:
        N/A
4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
    N/A
--$)S
***************************************************************************/
void UART_F_InitComProtocol()
{
    UART_E_PortID e_PortID;
    CSL_UartRegsOvly pt_RegSet;

    for(e_PortID = USB_UART_ID; e_PortID < NUM_OF_UARTS; e_PortID++)
    {
        pt_RegSet = UART_at_ChannelDBTable[e_PortID].pt_RegSet;
        CSL_FINST(pt_RegSet->LCR, UART_LCR_WLS, 8BITS);
        CSL_FINST(pt_RegSet->LCR, UART_LCR_STB, 1BIT);
        CSL_FINST(pt_RegSet->LCR, UART_LCR_EPS, EVEN);
        CSL_FINST(pt_RegSet->LCR, UART_LCR_PEN, DISABLE);
        CSL_FINST(pt_RegSet->LCR, UART_LCR_SP , DISABLE);
        CSL_FINST(pt_RegSet->LCR, UART_LCR_BC , DISABLE);

        /* modem control register */
        pt_RegSet->MCR = CSL_FMKT(UART_MCR_RTS,DISABLE)       /* RTS control       */
                                | CSL_FMKT(UART_MCR_LOOP,DISABLE) /* loopback mode    */
                                | CSL_FMKT(UART_MCR_AFE,DISABLE); /* auto flow enable */

    }

    return;
}
/***************************************************************************
--$(S
1. CSU Name:                                     CSU#
2. CSU Purpose:
3. Input/Output Data Elements:
    Input data elements:
        N/A
    Output data elements:
        N/A
4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
    N/A
--$)S
***************************************************************************/
void UART_F_DefineInterrupts()
{
    UART_E_PortID e_PortID;
    CSL_UartRegsOvly pt_RegSet;

    for(e_PortID = USB_UART_ID; e_PortID < NUM_OF_UARTS; e_PortID++)
    {
        pt_RegSet = UART_at_ChannelDBTable[e_PortID].pt_RegSet;
        /* Allows access to the receiver buffer register (RBR), the transmitter holding register (THR), and the
            interrupt enable register (IER) selected. At the address shared by RBR, THR, and DLL, the CPU can
            read from RBR and write to THR. At the address shared by IER and DLH, the CPU can read from and
            write to IER. */
        CSL_FINS(pt_RegSet->LCR, UART_LCR_DLAB, 0);
        CSL_FINST(pt_RegSet->PWREMU_MGMT, UART_PWREMU_MGMT_FREE, STOP);

        pt_RegSet->IER = CSL_FMKT(UART_IER_EDSSI, DISABLE )             /* Modem Status */
                                    |   CSL_FMKT(UART_IER_ELSI , ENABLE )    /* Line Status */
                                    |   CSL_FMKT(UART_IER_ETBEI, DISABLE )   /* Tx IRQ       */
                                    |   CSL_FMKT(UART_IER_ERBI , ENABLE);   /* Rx IRQ       */

    }

    C64_enableIER(C64_EINT4 | C64_EINT5 | C64_EINT6);

    return;
}
/***************************************************************************
--$(S
1. CSU Name:                                     CSU#
2. CSU Purpose:
3. Input/Output Data Elements:
    Input data elements:
        N/A
    Output data elements:
        N/A
4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
    N/A
--$)S
***************************************************************************/
void UART_F_Uart0IrqHandle(Uint32 u32_Param)
{
    UART_u32_IrqCounter[u32_Param]++;
    UART_F_UartRxHandler((UART_E_PortID)u32_Param);
    //SWI_post(&Swi_Uart0Rx);

    return;
}
/***************************************************************************/
void UART_F_Uart1IrqHandle(Uint32 u32_Param)
{
    UART_u32_IrqCounter[u32_Param]++;
    UART_F_UartRxHandler((UART_E_PortID)u32_Param);
    //SWI_post(&Swi_Uart1Rx);

    return;
}
/***************************************************************************/
void UART_F_Uart2IrqHandle(Uint32 u32_Param)
{
    UART_u32_IrqCounter[u32_Param]++;
    UART_F_UartRxHandler((UART_E_PortID)u32_Param);
    //SWI_post(&Swi_Uart2Rx);

    return;
}
/***************************************************************************
--$(S
1. CSU Name:                                     CSU#
2. CSU Purpose:
3. Input/Output Data Elements:
    Input data elements:
        N/A
    Output data elements:
        N/A
4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
    N/A
--$)S
***************************************************************************/
void UART_F_SwiUart0RxHandler()
{
    UART_F_UartRxHandler(USB_UART_ID);
    return;
}
/***************************************************************************/
void UART_F_SwiUart1RxHandler()
{
    UART_F_UartRxHandler(GPS_UART_ID);
    return;
}
/***************************************************************************/
void UART_F_SwiUart2RxHandler()
{
    UART_F_UartRxHandler(RS232_UART_ID);
    return;
}
/***************************************************************************
--$(S
1. CSU Name:                                     CSU#
2. CSU Purpose:
3. Input/Output Data Elements:
    Input data elements:
        N/A
    Output data elements:
        N/A
4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
    N/A
--$)S
***************************************************************************/
void UART_F_UartRxHandler(UART_E_PortID e_PortID)
{
    UART_E_IrqType e_IrqType;
    CSL_UartRegsOvly pt_CurrRegSet;
    Uint8 u8_IPend = 0;

    pt_CurrRegSet = UART_at_ChannelDBTable[e_PortID].pt_RegSet;

    e_IrqType = (UART_E_IrqType)CSL_FEXT(pt_CurrRegSet->IIR, UART_IIR_INTID);
    do
    {
        switch(e_IrqType)
            {
            case ITY_LineStatus   :
                UART_u32_IrqProblemCounter[e_PortID]++;
                UART_F_HandleLineStatusError(e_PortID);
                break;
            case ITY_RecDataReady :
                UART_u32_IrqRxCounterDR[e_PortID]++;
                UART_F_ReadReceiveDataBuffer(e_PortID);
                break;
            case ITY_RecTimeOut   :
                UART_u32_IrqRxCounterTO[e_PortID]++;
                UART_F_ReadReceiveDataBuffer(e_PortID);
                break;
            case ITY_TxHoldEmpty :
                UART_F_SendTxFifo(e_PortID);
                UART_u32_IrqTxCounter[e_PortID]++;
                break;
            default:
                UART_u32_DefaultCounter[e_PortID]++;
                break;
        }

        u8_IPend = CSL_FEXT(pt_CurrRegSet->IIR, UART_IIR_IPEND);
        e_IrqType = (UART_E_IrqType)CSL_FEXT(pt_CurrRegSet->IIR, UART_IIR_INTID);

    } while((u8_IPend == CSL_UART_IIR_IPEND_PEND) || e_IrqType);

    return;
}

/***************************************************************************
--$(S
1. CSU Name:                                     CSU#
2. CSU Purpose:
3. Input/Output Data Elements:
    Input data elements:
        N/A
    Output data elements:
        N/A
4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
    N/A
--$)S
***************************************************************************/
void UART_F_ReadReceiveDataBuffer(UART_E_PortID e_PortID)
{
    CSL_UartRegsOvly pt_CurrRegSet;
    Uint8 *pu8_RecBuffer, u8_MaxIterations ;
    Uint16 u16_WriteIndex;
    Uint32 u32_BufferSize;

    pt_CurrRegSet    = UART_at_ChannelDBTable[e_PortID].pt_RegSet;
    pu8_RecBuffer    = UART_at_ChannelDBTable[e_PortID].Buffer[FIFO_RX];
    u16_WriteIndex    = UART_at_ChannelDBTable[e_PortID].Indexes[FIFO_RX][WRITE_INDEX];
    u32_BufferSize   = UART_at_ChannelDBTable[e_PortID].u32_CycBuffersize;
    u8_MaxIterations = UART_COMPONENT_FIFO_SIZE;

    while( (CSL_FEXT(pt_CurrRegSet->LSR, UART_LSR_DR) == CSL_UART_LSR_DR_READY) && (u8_MaxIterations--))
    {
        UART_u32_BytesReceived[e_PortID]++;
        pu8_RecBuffer[u16_WriteIndex] = CSL_FEXT(pt_CurrRegSet->RBR, UART_RBR_DATA);
        u16_WriteIndex = ((u16_WriteIndex + 1) % u32_BufferSize);
    }

    UART_at_ChannelDBTable[e_PortID].Indexes[FIFO_RX][WRITE_INDEX] = u16_WriteIndex;

    return;
}
/***************************************************************************
--$(S
1. CSU Name:                                     CSU#
2. CSU Purpose:
3. Input/Output Data Elements:
    Input data elements:
        N/A
    Output data elements:
        N/A
4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
    N/A
--$)S
***************************************************************************/
Bool UART_F_SendData(UART_E_PortID e_PortID, Uint8 *pu8_buffer, Uint16 u16_Length)
{
    Bool b_RetVal = TRUE;
    Uint8 *pu8_DataSource = pu8_buffer;
    Uint8 *pu8_DataDest            = UART_at_ChannelDBTable[e_PortID].Buffer[FIFO_TX];
    Uint16 u16_WriteIndex            = UART_at_ChannelDBTable[e_PortID].Indexes[FIFO_TX][WRITE_INDEX];
    Uint16 u16_ReadIndex            = UART_at_ChannelDBTable[e_PortID].Indexes[FIFO_TX][READ_INDEX];
    Uint32 u32_CycBuffSize         = UART_at_ChannelDBTable[e_PortID].u32_CycBuffersize;
    Uint16 u16_VirtualReadIndex;

    if(u16_ReadIndex <= u16_WriteIndex)
    {
        u16_VirtualReadIndex = u16_ReadIndex + u32_CycBuffSize;

    }
    else
    {
        u16_VirtualReadIndex = u16_ReadIndex;
    }

    if((u16_WriteIndex + u16_Length) >= u16_VirtualReadIndex)
    {
        return FALSE;
    }

    while(u16_Length--)
    {
        *(pu8_DataDest+u16_WriteIndex) = *pu8_DataSource;
        pu8_DataSource++;
        u16_WriteIndex = (u16_WriteIndex + 1) % u32_CycBuffSize;
    }

    UART_at_ChannelDBTable[e_PortID].Indexes[FIFO_TX][WRITE_INDEX] = u16_WriteIndex;

    return b_RetVal;
}
/***************************************************************************
--$(S
1. CSU Name:                                     CSU#
2. CSU Purpose:
3. Input/Output Data Elements:
    Input data elements:
        N/A
    Output data elements:
        N/A
4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
    N/A
--$)S
***************************************************************************/
void UART_F_SendTxFifo(UART_E_PortID e_PortID)
{
    Uint8 u8_i, *pu8_DataSource;
    Uint16 u16_ReadIndex, u16_WriteIndex, u16_VirtualWriteIndex, u16_len;
    Uint32 u32_CycBufSize;
    CSL_UartRegsOvly pt_CurrRegSet;

    pu8_DataSource = UART_at_ChannelDBTable[e_PortID].Buffer[FIFO_TX];
    u16_WriteIndex = UART_at_ChannelDBTable[e_PortID].Indexes[FIFO_TX][WRITE_INDEX];
    u16_ReadIndex = UART_at_ChannelDBTable[e_PortID].Indexes[FIFO_TX][READ_INDEX];
    u32_CycBufSize = UART_at_ChannelDBTable[e_PortID].u32_CycBuffersize;
    pt_CurrRegSet = UART_at_ChannelDBTable[e_PortID].pt_RegSet;
    u8_i = 0;

    /* Find out how many bytes are there to send */
    if(u16_WriteIndex < u16_ReadIndex )
    {
        u16_VirtualWriteIndex = u16_WriteIndex + u32_CycBufSize;
    }
    else
    {
        u16_VirtualWriteIndex = u16_WriteIndex;
    }
    u16_len = u16_VirtualWriteIndex - u16_ReadIndex;

    /* Wait for Tx Fifo Empty flag */
    if(CSL_FEXT(pt_CurrRegSet->LSR, UART_LSR_TEMT) == CSL_UART_LSR_TEMT_EMPTY)
    {
        //u32_HwiStatus = HWI_disable();
        /* Limiting # of bytes to send */
        while( (u8_i < UART_COMPONENT_FIFO_SIZE) && (u8_i < u16_len) )
        {
            /* Indication */
            UART_u32_BytesSent[e_PortID]++;

            /* Tx the Byte */
            CSL_FINS(pt_CurrRegSet->THR, UART_THR_DATA, pu8_DataSource[u16_ReadIndex]);

            /* "Yaanu" Tx the Byte (Write to Scratch pad)*/
            //CSL_FINS(pt_CurrRegSet->SCR, UART_SCR_SCR, pu8_DataSource[u16_ReadIndex]);

            /* Update Local Counters */
            u8_i++;
            u16_ReadIndex = ((u16_ReadIndex + 1) % u32_CycBufSize);
        }

        UART_at_ChannelDBTable[e_PortID].Indexes[FIFO_TX][READ_INDEX] = u16_ReadIndex;
    }
    else
    {
        UART_u32_StillSending[e_PortID]++;
    }

    return;
}/***************************************************************************
--$(S
1. CSU Name: UART_F_ConnectSerialToGPS                                    CSU#
2. CSU Purpose:

3. Input/Output Data Elements:
    Input data elements:

    Output data elements:

4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
        None
--$)S
***************************************************************************/
void UART_F_ConnectSerialToGPS()
{

    return;
}
/***************************************************************************
--$(S
1. CSU Name: UART_F_GetBufferFreeSpace                            CSU# 40-40-60
2. CSU Purpose:
        Return a buffer free space
    calculate the output buffer size.
3. Input/Output Data Elements:
    Input data elements:
        1.UART_e_PortID e_UartID - The relevant SW buffer
    Output data elements:
        1.Uint16 - How many free bytes are there
4. Algorithm & Logic Flow:
        switch according to Buffer ID.
5. Error Handling & Limitations:
        N/A
--$)S
***************************************************************************/
Uint16 UART_F_GetBufferFreeSpace(UART_E_PortID e_UartID)
{

    Uint16 u16_len=0;
#ifdef REV_B_COMPATIBILITY
    switch(e_UartID)
    {
        case GPS_UART_ID:
            if(UART_u16_OutputGPSBufferWriteIndex >UART_u16_OutputGPSBufferReadIndex)
            {
                u16_len = UART_u16_OutputGPSBufferWriteIndex - UART_u16_OutputGPSBufferReadIndex;
            }
            else
            {
                u16_len = GPSBUFSIZE + UART_u16_OutputGPSBufferWriteIndex - UART_u16_OutputGPSBufferReadIndex;
            }
            break;
        case RS232_UART_ID:
            if(UART_u16_OutputRS232BufferWriteIndex >UART_u16_OutputRS232BufferReadIndex)
            {
                u16_len = UART_u16_OutputRS232BufferWriteIndex - UART_u16_OutputRS232BufferReadIndex;
            }
            else
            {
                u16_len = UARTBUFSIZE + UART_u16_OutputRS232BufferWriteIndex - UART_u16_OutputRS232BufferReadIndex;
            }
            break;
        case USB_UART_ID:
            if(UART_u16_OutputUSBBufferWriteIndex >UART_u16_OutputUSBBufferReadIndex)
            {
                u16_len = UART_u16_OutputUSBBufferWriteIndex - UART_u16_OutputUSBBufferReadIndex;
            }
            else
            {
                u16_len = UARTBUFSIZE + UART_u16_OutputUSBBufferWriteIndex - UART_u16_OutputUSBBufferReadIndex;
            }
            break;
    }
#else
    Uint16 u16_ReadIndex, u16_WriteIndex;
    Uint32 u32_CycBufSize;

    u16_WriteIndex = UART_at_ChannelDBTable[e_UartID].Indexes[FIFO_TX][WRITE_INDEX];
    u16_ReadIndex = UART_at_ChannelDBTable[e_UartID].Indexes[FIFO_TX][READ_INDEX];
    u32_CycBufSize = UART_at_ChannelDBTable[e_UartID].u32_CycBuffersize;

    if(u16_WriteIndex >u16_ReadIndex)
    {
        u16_len = u16_WriteIndex - u16_ReadIndex;
    }
    else
    {
        u16_len = u32_CycBufSize + u16_WriteIndex - u16_ReadIndex;
    }

#endif
    return u16_len;

}
/***************************************************************************
--$(S
1. CSU Name:                             CSU#
2. CSU Purpose:

3. Input/Output Data Elements:
    Input data elements:

    Output data elements:

4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
        N/A
--$)S
***************************************************************************/
void UART_F_TxTsk()
{
    UART_E_PortID e_PortID;

    SEM_pend(&SEM_Tx, SYS_FOREVER);
    while(1)
    {
        for(e_PortID = USB_UART_ID; e_PortID < NUM_OF_UARTS; e_PortID++)
        {
            UART_F_SendTxFifo(e_PortID);
        }
        TSK_sleep(1);
    }

}
/***************************************************************************
--$(S
1. CSU Name:                             CSU#
2. CSU Purpose:

3. Input/Output Data Elements:
    Input data elements:

    Output data elements:

4. Algorithm & Logic Flow:

5. Error Handling & Limitations:
        N/A
--$)S
***************************************************************************/
Uint32 UART_F_HandleLineStatusError(UART_E_PortID e_PortID)
{
    Uint32 u32_LineStatus, u32_IIRImage = 0;
    Uint8 u8_TempByte, u8_MaxIterations;
    CSL_UartRegsOvly pt_CurrRegSet;

    pt_CurrRegSet = UART_at_ChannelDBTable[e_PortID].pt_RegSet;

    u32_LineStatus = pt_CurrRegSet->LSR;

    /* If its an overrun error */
    if(u32_LineStatus & CSL_UART_LSR_OE_MASK)
    {

    }
    if(u32_LineStatus & CSL_UART_LSR_RXFIFOE_MASK)
    {
        /* If its an parity framing or break */
        if(u32_LineStatus & CSL_UART_LSR_PE_MASK)
        {

        }
        if(u32_LineStatus & CSL_UART_LSR_FE_MASK)
        {

        }
        if(u32_LineStatus & CSL_UART_LSR_BI_MASK)
        {

        }

        /* Prepare iteration limits for Clearing erroneous bytes */
        u32_IIRImage = ( (pt_CurrRegSet->IIR) & (0x0F) );
        u8_MaxIterations = UART_COMPONENT_FIFO_SIZE;

        /* Clear All erroneous bytes */
        /* while IIR is 0110 - the LSB (0) means IRQ pending, the 3 MSB (011) means Line Status Interrupt */
        while((u32_IIRImage == CSL_UART_IIR_INTID_CTI) && (u8_MaxIterations--) )
        {
            /* Read the byte*/
            u8_TempByte = CSL_FEXT(pt_CurrRegSet->RBR, UART_RBR_DATA);
            /* Throw the byte */
            CSL_FINS(pt_CurrRegSet->SCR, UART_SCR_SCR, u8_TempByte);
            /* Check the IIR */
            u32_IIRImage = ( (pt_CurrRegSet->IIR) & (0x0F) );
        }
    }

    return u32_LineStatus;
}

0 Brad Griffis over 15 years ago in reply to Yoav Gold

TI__Guru*** 125430 points

Please set DMAMODE1=1 in your code. Although you have not seen a difference in your previous tests, that is the recommended setting.

0 Yoav Gold over 15 years ago in reply to Brad Griffis

Prodigy 250 points

Hi brad,

I tested the time delay between bytes sent to the System using a Tektronix scope.
It looks like there is a 15~20 Micro delay between bytes. Ill try it with a delay.
Is there some spec specifying what is the minimum delay required to avoid these issues?

I also changed the DMA mode to 1.

Any other Ideas?

Thanks,
Yoav.

0 Yoav Gold over 15 years ago in reply to Yoav Gold

Prodigy 250 points

I inserted a 1 milisec delay between bytes (Varifyed it with a scope).
There was no improvment in the situation

Yoav

0 Brad Griffis over 15 years ago in reply to Yoav Gold

TI__Guru*** 125430 points

Sorry to hear that. Can you reproduce the issue on an EVM? If not, then perhaps that will clue you/us into a hardware issue. If so, that gives something that TI can easily reproduce to get to the root of the matter. Perhaps you could just transmit dummy data to the terminal (e.g. Tera Term) and then do File -> Send to replicate the "full duplex nature" of the issue.

0 Yoav Gold over 15 years ago in reply to Brad Griffis

Prodigy 250 points

Hi brad,

Well, I managed to reproduce this issue on the EVM...Ill try to prepare a complete project that you will be able to compile and run.

About the test you are offering, This is exactly the way I'm holding my tests, I'm constantly sending data out from the DSP via a specific port, and trying to send data in using a terminal. then I'm using SW Breakpoints OR Counters to see if these errors occured. I also tried it with a bootable version (on our HW) and got the same results so this doesnt look like an emulation issue.

Thanks for all the help

Yoav

0 Yoav Gold over 15 years ago in reply to Yoav Gold

Prodigy 250 points

OK,

I prepared a portable project that is EVM compatible, Where can I upload it to for you to take a look at it?

0 Mukul Bhatnagar over 15 years ago in reply to Yoav Gold

TI__Guru* 84325 points

Hi Yoav

Would it be easy to hand this off to your local TI support team? If so , please do so and they will forward it to us.

Regards

Mukul

0 Yoav Gold over 15 years ago in reply to Mukul Bhatnagar

Prodigy 250 points

Its been done

Yoav

0 Yoav Gold over 15 years ago in reply to Yoav Gold

Prodigy 250 points

Hi,

Did you get a copy of our project? Were you able to run it on your EVM? Did you notice the problem?

Yoav

0 Mukul Bhatnagar over 15 years ago in reply to Yoav Gold

TI__Guru* 84325 points

Hi Yoav

Yes, we did get the project. I was not able to allocate time to do spend much time debugging this, will be doing so in the coming week. Regret the delay in turning this around.

Regards

Mukul

0 Mukul Bhatnagar over 15 years ago in reply to Mukul Bhatnagar

TI__Guru* 84325 points

Hi Yoav

No significant updates still on this issue. I am able to reproduce this , but have not been able to pin point on the root cause. The only small observation that I have was that it seemed that I could make the test fail (hit the breakpoint) more easily/quickly if I had a memory window opened in CCS, for the UART tx/rx buffers. If the memory windows were not open , the failure took longer to occur.

I will keep you posted on any additional updates/findings on this.
Regards

Mukul

0 Yoav Gold over 15 years ago in reply to Mukul Bhatnagar

Prodigy 250 points

Hi mukul,

I guess no news yet ?

Anyway, regarding the memory window, We also saw that working with memory windows\breakpoints can cause all sorts of things.
In our particular case, We encountered the problem even when we operated from a bootable version (No Emulation, loading a flash burned version) so even if this happens more often while you have a memory window open, I'm not sure that this is related.

Thanks for Keeping me posted,

Yoav.

0 jc-ti over 15 years ago in reply to Yoav Gold

TI__Mastermind 27585 points

Yoav, sorry for the long delay in getting your problem solved. We were able to reproduce your issue on Quickturn and found the issue.

The problem is in your UART_F_SendTxFifo function. You use the CSL macro "CSL_FINS" to write to the THR. However, this is a Read-Modify-Write macro, meaning that every time you wrote to the THR, it was first reading the RBR (they share the same address).

When an RX interrupt occurred during these writes to THR, the macro would read and clear the interrupt before you entered the RX Handler ISR, which explains why the IIR said there was no interrupt pending by the time you got there. Even when you went ahead and tried to read the data in this case, it had already been read out of the FIFO by the CSL macro during the writes, which explains why you seemed to skip a byte sometimes.

To fix it, change the following line:

CSL_FINS(pt_CurrRegSet->THR, UART_THR_DATA, pu8_DataSource[u16_ReadIndex]);

to this:

pt_CurrRegSet->THR = pu8_DataSource[u16_ReadIndex];

We verified everything works on the EVM with this change, so that should fix it.

Let us know if you have any more questions.

Jeff

0 Yoav Gold over 15 years ago in reply to jc-ti

Prodigy 250 points

Hi Jeff (and Brad and Mukul)

All of us guys here are quite shocked that we missed it, because we all assumed that we are clearing the RBR while we are Transmitting only we took this macro for granted and didnt take time to realize its a Read-Modify-Write.

So first, Thanks alot, We ran a few tests and we are not experiancing any data loss.

Second, after having a quick look into my debug variables, I think I saw what looked like unidentifyied interrupts are still arriving only now they are not interfering with the data.

Ill Look further into it and give and Ill report If I see this issue again (I didnt have time to do a complete checkup today).

anyway, Thanks, , This helps us a lot.

Yoav

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Receiving unidentified interrupts from UART on C6747