Hidden limit on the byte-counts when cache-invalidating

Daniel Zhou

Hello,

In my application, I need to invalidate a big buffer, 2 Mega bytes in size, from the cache. When I ran CACHE_wbInvL1d(addr, size, CACHE_FENCE_WAIT), it does not seem to work as expected. Cache write-back still happens long after the invalidating. So I ended up having to either invalidate/write-back the whole cache or invalidate/write-back 32k or 64k bytes at a time.

Is there a limit on the size of the buffer to be invalidated from the cache?

Thanks,

Daniel

over 11 years ago

0 Steven Ji over 11 years ago

TI__Genius 12065 points

Daniel,

Please take a look at C66x DSP cache user guide which mentions that "Note that the maximum byte count that

can be specified is 4 × 65 535." That is, one L1D or L2 cache operation can operate on at most 256K bytes. If the external memory buffer to be operated on is larger, multiple cache operations have to be issued.

0 Ralf Goebel over 11 years ago

Genius 3715 points

Hi Daniel,

I think it's better to use the SYS/BIOS cache API instead: Cache_inv() / Cache_wbInv() / Cache_wb()

This API will handle L1 and L2 cache and the buffer size can be large.

There are also silicon bugs which are not covered by the CSL cache API (C6678: Advisory 7, 22 and 27).

Ralf

0 Daniel Zhou over 11 years ago in reply to Ralf Goebel

Intellectual 310 points

Thanks Steven and Ralf.

Ralf, can you give me a link to the silicon bugs that you mentioned?

Daniel

0 Clemens Eisserer over 11 years ago in reply to Daniel Zhou

Expert 2430 points

http://www.ti.com/lit/er/sprz334f/sprz334f.pdf

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Hidden limit on the byte-counts when cache-invalidating