dm8168 operating frequency

I guess you are using DVR RDK release.  Release package includes a PLL calculator excel sheet in docs/userguide folder (DM816x_FAPLL.xls). This provides the values required by these variables for various frequencies.

hello Sivagamy,

thanks for your reply.

After trying following, I didn't find the your mentioned file. Could you help to clarify ?

[~/Projects/TI-8168/DVRRDK_03.00.00.00_dvr] $ find ./dvr_rdk/ -name "DM816x_FAPLL.xls"
[~/Projects/TI-8168/DVRRDK_03.00.00.00_dvr] $ find ./ti_tools/ -name "DM816x_FAPLL.xls"

3.0 release does not have this sheet.

Its part of DVRRDK_04.00.00.03\dvr_rdk\docs\UserGuides\DM816x_FAPLL.xls

 3.0 uboot uses PLL multiplication factor of 64 for the Main PLL.

This will will result in the Main PLL operating at 1728MHz (64*27). The FAPLL operation is marginal at 1728MHz and this can result in an issue with the PLL locking at higher temperatures of operation. So, multiplication factor of 64 is not recommended. This is fixed in later dvr rdk releases.

Its better that you update uboot pll setting functions as per 4.0 release to use multiplication factor of 56 which is what the excel sheets uses. Please contact  your FAE to get latest dvr rdk releases and use as reference.

hello Sivagamy,

 thanks for your reply.

This will will result in the Main PLL operating at 1728MHz (64*27). The FAPLL operation is marginal at 1728MHz and this can result in an issue with the PLL locking at higher temperatures of operation.

==> did you know what problem will be caused by this issue(PLL locking)  ??

Possible - Check frequency range in TRM.

A specific commit on TI81xx uboot here - http://arago-project.org/git/projects/?p=u-boot-omap3.git;a=commit;h=7285eeefaa5a63eb6c6d515dd2bbc0b7394bd9d6

Note that this patch cannot be applied directly on dvr rdk uboot as there are dvr board specific changes. You will have to selectively take the changes.

hello Sivagamy,

 thanks for your reply.

Possible - Check frequency range in TRM.

- did you mean it may cause hang in host ?

hello Sivagamy,

I have one more question.

in following case, who is the bottleneck.

ARM(1.2GHz)  --  DDR(796MHz)   , bottleneck is DDR ??

DSP(1GHz)  --  DDR(796MHz)      , bottleneck is DDR ??

M3(280MHz)  --  DDR(796MHz)     , bottleneck is M3 ??

are the above correct ??

1. did you mean it may cause hang in host ?

--> Possible.

2. in following case, who is the bottleneck.

ARM(1.2GHz)  --  DDR(796MHz)   , bottleneck is DDR ??

DSP(1GHz)  --  DDR(796MHz)      , bottleneck is DDR ??

M3(280MHz)  --  DDR(796MHz)     , bottleneck is M3 ??

--> Depends on use case. Set M3 to 274MHz which is recommended. This the max recommended setting as per dvr rdk tests. Refer latest release (4.0 or later) dvr rdk uboot code.

hello  Sivagamy

thanks for your reply.

we have a phenomenon in a customized board which is there's no response in telnet, console, no video. It looks like A8 and M3 hang.

Currently, we have no idea about this. Did you have any suggestion??

This does not look like a S/W issue. Similar phenmenon is possible if there is power supply / hardware issues.

Please loop in your FAE to get help from H/W support team.

Sivagamy Govindasamy said:

Possible - Check frequency range in TRM.

A specific commit on TI81xx uboot here - http://arago-project.org/git/projects/?p=u-boot-omap3.git;a=commit;h=7285eeefaa5a63eb6c6d515dd2bbc0b7394bd9d6

Note that this patch cannot be applied directly on dvr rdk uboot as there are dvr board specific changes. You will have to selectively take the changes.

hello Sivagamy,

    Thanks for your reply.

As your speaking, the parameters was the same as those in uboot inrdk4.1. After checking ./arch/arm/include/asm/arch-ti81xx/clocks_ti816x.h. I found that the DSP was 1GHz.

/* DSP -> 1000 MHz*/
#define MAIN_INTFREQ1 0xC
#define MAIN_FRACFREQ1 0x189374
#define MAIN_MDIV1 0x1

Q1.   if I want 800MHz, how do I modify these?  I didn't see any info in DM816x_FAPLL.xls.

hello TI friends,

  Is it possible to change the frequency of ARM/M3/DSP dynamically?