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regarding TSIP interface

Pradeep Naru
Intellectual 300 points
Other Parts Discussed in Thread: TMS320C6678

Hi,

          TSIP interface is implementing between TMS320C6678 DSP and FPGA in our board.data rate to be transferred between DSP and FPGA is 160 Kbps(320 samples per sec).please suggest an idea how can TSIP can be customized to support this data rate.(as originally it supports 8.192Mbps on each link)

Regards,

Pradeep N.

  • 0
    TI__Genius 12065 points

    Pradeep,

    The primary purpose of TSIP is designed for telecom serial data streams. And the standard data rate is 8.192 Mbps with 8 links active and all 1024 time slots are enabled.

    You may try to play with channel bitmap to see if you could disable some time slots to coordinate with your customized data rate. But please note the clock input to TSIP is still required to be 8.192MHz or 16.384MHz with frame sync input to be 8KHz (1/125us).