Hello All,
At the beginning I want to notice I'm working with the TMS320C6671 DSP. The Goal I want to reach is correctly program the DDR3 PLL controller. I use the SPRS756D (TMS320C6671 dsp), SPRUGV8C (keystone DDR3 emif), SPRUGV2F (keystone PLL), SPRABL2A (KeyStone DDR3 Initialization).
I would like to ask for some help in the PLL controller subject. I'm a little bit confused while checking the documentations. It's probably because I missed something.
The problem I have is I'm not sure how to program the BWADJ value in the PLL control registers.
The confusion begins while reading the SPRS756D. The "DDR3 PLL Block Diagram" (page 148) uses "PLLM" acronym. At this point (while looking at the diagram) I understand that the "PLLM" defines the numeric value of the multiplier. But on the next page there is description of the "DDR3 PLL Control Register 0" where the acronym is used to describe the register field ("A 13-bit bus that selects the values for the multiplication factor"). I didn't found the description how the register field value selects the multiplier. From the "KeyStone DDR3 Initialization" (2. DDR3 Controller Configuration) I understand that the value of 0 means multiplier 1 (similar as the PLLM field in the PLLM register of the main PLL in the DSP).
The main problem for me is that the PLLM acronym is also used to describe the desired value of the "BWADJ" fields in the DDR3 PLL Control Registers.
BWADJ[11:8] and BWADJ[7:0] are located in DDR3PLLCTL0 and DDR3PLLCTL1 registers. The combination (BWADJ[11:0]) should be programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value). Example: PLLM=15, then BWADJ=7
From this point it looks like the value of the BWADJ [11:0] should be just the PLLM[12:0] (register field !) shifted 1 right (divided by 2 rounded down).
But in the "KeyStone DDR3 Initialization" there is a sample to configure the DDR3 controller which programs the DDR3 PLL to generate a 666.67MHz clock (for DDR3-1333 operation) from an input clock of 66.667 MHz. In this case the divider value is 1 (0 in the register) and the multiplier is 20 (19 in the register). But the BWADJ value is counted this way : PLL2_BWADJ = ((PLL2_PLLM + 1) >> 1) - 1. What gives value 9. This particular value fits to this what I understood from the description BWADJ description. But from my understanding counting the BWADJ should look like this PLL2_BWADJ = PLL2_PLLM >> 1 (shifting right makes it half of the value rounded down). The original equation don't fit to my understanding. If the PLL2_PLLM will be 20 (the result will be also 9).
I also found a post :
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/117294/417986.aspx#417986
which describes how to program the main PLL (where also is a BWADJ field) I assume that there is the same convention (the BWADJ field in the main PLL is described in the same way as in the DDR3 PLL)
> Set BWADJ = [7:0] = (PLLM+1)/2 = 0x20 in MAINPLLCTL0 register.
The questions in this case are.
I want to multiply the input DDR3CLK clock by n/2 (because of the final "2" divider and custom "1" divider).
1. Should The PLLM field value in the DDR3PLLCTL0 register be (n-1)?
2. What equation should I use to count BWADJ [11:0] value?
I assume that the answer for first question is "Yes" so I define a pllm_val as (n - 1) so the sample equation are :
- BWADJ[11:0] = pllm_val / 2 (my understanding of the documentation)
- BWADJ[11:0] = (pllm_val + 1) / 2 (e2e verified answer post)
- BWADJ[11:0] = ((pllm_val + 1) / 2) - 1 (SPRABL2A)
I'll be very thankful for some suggestions.
Regards Lukasz
