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Cache coherency of AM3874

Michi Yama
Guru 10030 points

Other Parts Discussed in Thread: AM3874

Hi,

I have one question for cache coherency.

I don't know well the internal cache of AM3874. But my customer has cache coherency issue now.

So I would like to know what CP15 command is needed for keeping cache coherency.

I checked the ARM architecture manual. But I could not find any command for keeping coherency.

Is there any special commands for keeping cached coherency?

Please advise me.

Best regards,

Michi

  • 0
    TI__Guru**** 170625 points

    Hi Michi,

    This is what I found regarding cache coherency in Cortex-A8 ARM:

    http://e2e.ti.com/support/embedded/starterware/f/790/t/260608.aspx

    The cache operations are controlled from the C7 register of the CP15 registers group:

    http://processors.wiki.ti.com/index.php/Cortex-A8_Architecture#Cortex-A8_CP15_Register_Groups

    http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344k/Babhejba.html

    Regards,
    Pavel

  • 0
    Guru 31670 points

    Dear Michi-san,

    There won't be any separate command available to maintain cache-coherency. Its more of a software problem and the software needs to take care when caching is enabled for a particular region. Can you describe what is the exact issue that your customer is facing?