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C6670 PCIe Legacy Interrupt

g.f.
Guru 15520 points

Hi,

I have question about KeyStone PCIe Interrupt.

In our system C6670 is Endpoint and other CPU device is Root Complex.
I'm using PCIe Legacy Interrupt A and
expecting one interrupt will be generated from Endpoint to Root Complex
at the timing which I expected.

But after one INTA has been generated to RC, another INTA have been generated to RC
after 1 byte access to PCI data space from EP which I didn't expected.

INTA is generated as follow:
(refer to PCIe TRM page.62 "2.14.2.1 Legacy Interrupt Generation in EP Mode")

////////////////////////////////////////////////////////////////////////////
#define LEGACY_A_IRQ_ENABLE_SET        *(volatile unsigned int*)0x21800188
#define EP_IRQ_SET                     *(volatile unsigned int*)0x21800064
#define EP_IRQ_CLR                     *(volatile unsigned int*)0x21800068

1. LEGACY_A_IRQ_ENABLE_SET = 0x1;
2. EP_IRQ_SET = 0x1;
3. EP_IRQ_CLR = 0x1;
////////////////////////////////////////////////////////////////////////////

I didn't configure the above setting to the register when INTA have been
generated to RC after 1 byte access to PCI data space from EP.
What cause the INTA generation to the RC in this case?

By my recognition, INTA will be only generated if I cofigure the above
setting to the register. Is it wrong?
If anyone have an information, please give me an advise.

best regards,
g.f.

  • 0
    TI__Guru* 95265 points

    Yes the sequence is correct from the spec 2.14.2.1 Legacy Interrupt Generation in EP Mode. If you don't call this sequence again, I don't think INTA can be triggered the second time.

    How do you know that happened twice, the RC side's ISR handler entered twice? After the first INTA,

    1. LEGACY_A_IRQ_ENABLE_SET = 0x1;
    2. EP_IRQ_SET = 0x1;

     the EP_IRQ_STATUS should be set to "1"

    3. EP_IRQ_CLR = 0x1;

    the EP_IRQ_STATUS should be "0"

    Did you see EP_IRQ_STATUS came back to 1 when you find two INTA generated?

    Regards, Eric

  • 0 in reply to lding
    Guru 15520 points

    Hi Eric,

    Thank you for the reply.

    I understood how legacy interrupt occur.
    Thank you.

    Actually this question was from my customer.
    They said that the RC side's ISR handler entered twice.

    But now, this problem isn't happening.
    It's maybe RC side problem.
    But it's not happening now, so that we can't figure it out
    what caused this problem.

    So, I will close this post. Thank you for supporting me.

    best regards,
    g.f.