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C6678 PCIESS link training fail issue

Ali Kozan
Prodigy 30 points
Other Parts Discussed in Thread: CDCE62005

Hello people.

I have an issue about PCIe communication between a C6678 EVM and Xilinx Spartan 6 EVM. I'm connecting a TMDXEVM6678LE EVM to Xilinx SP605 EVM on PCIe port. In this set, DSP is RC and FPGA is EP. I'm running the PCIe example code in C6678 PDK coming with MCSDK 2.0 without any modification (I only modified PCIe mode variable as RC_mode, necessarily)

I have four Advantech TMDXEVM6678LE EVM boards. One of them is Rev. 0.2 (A101-1) and the others are Rev. 3.0 (A104-1). I'm using them with exactly same configuration, I mean the configuration switches on board (I enable PCIESS, set reference clock as the clock source on board).  When I connect Rev.0.2 one, link training part is done and link is up, but with the Rev. 3 one, I stuck at the link training part forever. I tried to change to another Rev.3 board but the result is same.

So my question is, what is the difference between these revisions of EVM's that affecting the PCIESS usage?

Edit: I had miswritten the board revisions, they've been corrected.

  • 0
    TI__Guru* 95265 points

    Ali,

    The latest MCSDK is 2.1.2.6 or PDK 1.1.2.6. The  PCIe example code in C6678 PDK is running at "no boot" mode, NOT PCIE boot mode.

    What is the board switch setting when you tested with FPGA? Can you put the board in no-boot mode?

    Regards, Eric

  • 0 in reply to lding
    Prodigy 30 points

    Hello Eric,

    Allright, I have the latest MCSDK version now, but result is the same.

    The board switch settings I've used in Rev 0.2 card are:

    SW3[1] = 1 (Little endian mode)

    SW3[4:2] = 0x101b (Boot device is I2C)

    SW4 and SW5[3:1] are not applicable here, they are for EMIF16 boot,
    anyway, the value is: SW5[3:1] : SW4[4:1] = 0x0000001b

    SW6[2:1] : SW5[4] = 0x110b (C66x DSP System PLL Configuration is adjusted to 100 MHz)

    SW6[4:3] = 0x11b (PCIe in Root Complex mode)

    SW9 = 0x11b (PCIe module is enabled)

     

    The board switch settings I've used in Rev 3.0 card are:

    SW3[1] = 1 (Little endian mode)

    SW3[4:2] = 0x101b (Boot device is I2C)

    SW5[1] : SW4[4:1] = 0x00000b (I2C Parameter index)

    SW5[2] = 0 (I2C is in Master mode)

    SW5[3] = 0 (PCIe reference clock from CDCE62005)

    SW5[4] = 1 (I2C Boot Device -> Boot from address 0x51)

    SW6[1] = 0 (I2C Boot Device -> Low speed)

    SW6[2] = 0 (Bit reserved with I2C Boot Device)

    SW6[4:3] = 0x10b (PCIe in Root Complex Mode)

    SW9 = 0x01b (PCIe module is enabled)

    I connect to these cards in a debug session on CCS, not loading the program to the I2C or sth.. By saying "no boot" mode, do you mean the "EMIF16 or emulation boot" ? I couldn't find anything written, related to "no-boot mode".

    Thanks in advance

    Ali

  • 0 in reply to Ali Kozan
    TI__Guru* 95265 points

    Please check http://processors.wiki.ti.com/index.php/TMDXEVM6678L_EVM_Hardware_Setup for no-boot switch pin setup.

    Regards, Eric

  • 0 in reply to lding
    Prodigy 30 points

    OK, I tried "no boot" mode on Rev. 3 board and again it failed.

    I found a difference between these board revisions about PCIe reference clock mux. In Rev. 0.2 board, there is no mux, just AC coupling capacitors are connected. In Rev. 3 board, there is a mux that I can select PCIe reference clock, AMC or local Clock generator.

    Interesting thing is, when I configure reference clock as AMC in my Rev. 3 board (and it's also configured as RC), link training is succeeded. It sounds awkward to me, is there any application of a PCIe communication that the reference clock is provided by EP?

    Xilinx Spartan 6 SP605 Board that I use have already had a bitstream on one of its on-board memory modules, I didn't prepare that bitstream, I've just been informed that the bitstream is working in EP mode, so I'm trying to verify the RC side (DSP board).

    I also tried a different test design. I've prepared a bitstream containing Microblaze processor and added "axi_pcie" IP core to my design. After that, I've build "axi_pcie" endpoint example project and loaded to FPGA. Again, only in AMC reference clock mode, my Rev.3 board says link is up, but this time, I've seen that SP605 board (EP) couldn't verify that link is up. However, this is another story.

    So this is the recent situation. Any suggestions?

    Thanks in advance

    Ali

  • 0 in reply to Ali Kozan
    TI__Guru* 95265 points

    Ali,

    All versions of the EVM that have the PCIe clock mux can operate either with the local on-board clock or with an external clock provided over the FCLK pins on the AMC connector. This mux can be controlled by writing to a register in the FPGA.

    In the ealier version of board (your Rev 0.2), the writing to FPGA register is done in IBL code. In the latest version of the EVM (Rev 3.0), it also has the ability to use a DIP switch to set this initial mux control register value. We don't have PCIE RC driver on 6678 EVM, many times the EVM is used as PCIE EP with a ATX PC, it requires a clock input from AMC, that is why we have a DIP switch to select clock source.

    Regards, Eric