Platform: OMAPL138
Reference: the readwrite example from DSPLink in the SDK
DSP side : I used EMIFA to connect a FPGA(LX30T) and via EDMA to transfer the data to DSP L2 RAM.
ARM side: I've modifyed the readwrite example and used "PROC_read" function to read the data from DSP L2 RAM.then i need to write the data to the disk (SATA,80G).
I found that the data received from DSP L2 RAM can be transfered via internet(UDP) but can't be recorded to disk; when i called the"system("umount /mnt/disk")" function, the program will stop here and have no return value. that means something has biocked when i have need to umount the disk ,but when i creat a buffer like that "mubuff[]={1,2,3,4,5,}" on the DSP side .everything will be OK. So I believe that when i used the EDMA and EMIFA,there are some conflicts to the SATA controller .but i can't find it.
//////////////////////////////////////////////////////program///////////////////////////////////////////
==============readwrite TSK===================
static Int tskReadwrite()
{
status = TSKRDWR_create (&info);
status = MSGQ_get (info->dspMsgqQueue, (MSGQ_Msg *) &msg, SYS_FOREVER) ;
status = MSGQ_free ((MSGQ_Msg) msg) ;
USTIMER_init();
C64_enableIER(C64_EINT6);
EMIFA_init();
AD_init();
DMAconfig();
*(volatile uint16_t*)(ADDR) = 1;
AD_EDMA_START;
return status;
}
=================readwrite.tcf====================
bios.HWI.instance("HWI_INT6").interruptSelectNumber = 8;//EDMA transfer completed
bios.HWI.instance("HWI_INT6").fxn = prog.extern("HWI_fxn");
bios.HWI.instance("HWI_INT6").useDispatcher = 1;
================ hwiFxn0 =======================
Void HWI_fxn(Void)
{
status = MSGQ_put (info->gppMsgqQueue, (MSGQ_Msg) msg) ;
if (status != SYS_OK)
{ MSGQ_free((MSGQ_Msg)msg);}
DMAconfig();
AD_EDMA_START;
*(volatile uint16_t*)(ADDR+((1)<<2)) = 1;
}
uint32_t EMIFA_init()
{
EVMOMAPL138_lpscTransition(PSC0, DOMAIN0, LPSC_EMIFA, PSC_ENABLE);
EVMOMAPL138_pinmuxConfig(PINMUX_EMIFA_NOR_REG_0, PINMUX_EMIFA_NOR_MASK_0, PINMUX_EMIFA_NOR_VAL_0);
EVMOMAPL138_pinmuxConfig(PINMUX_EMIFA_NOR_REG_1, PINMUX_EMIFA_NOR_MASK_1, PINMUX_EMIFA_NOR_VAL_1);
EVMOMAPL138_pinmuxConfig(PINMUX_EMIFA_NOR_REG_2, PINMUX_EMIFA_NOR_MASK_2, PINMUX_EMIFA_NOR_VAL_2);
EVMOMAPL138_pinmuxConfig(PINMUX_EMIFA_NOR_REG_3, PINMUX_EMIFA_NOR_MASK_3, PINMUX_EMIFA_NOR_VAL_3);
EVMOMAPL138_pinmuxConfig(PINMUX_EMIFA_NOR_REG_4, PINMUX_EMIFA_NOR_MASK_4, PINMUX_EMIFA_NOR_VAL_4);
EVMOMAPL138_pinmuxConfig(PINMUX_EMIFA_NOR_REG_5, PINMUX_EMIFA_NOR_MASK_5, PINMUX_EMIFA_NOR_VAL_5);
EVMOMAPL138_pinmuxConfig(PINMUX_EMIFA_NOR_REG_6, PINMUX_EMIFA_NOR_MASK_6, PINMUX_EMIFA_NOR_VAL_6);
EVMOMAPL138_pinmuxConfig(PINMUX_EMIFA_NOR_REG_7, PINMUX_EMIFA_NOR_MASK_7, PINMUX_EMIFA_NOR_VAL_7);
EMIFA->CE4CFG = (2 << 26) | (4 << 20) | (2 << 17) | (2 << 13) | (2 << 7) | (2 << 4) | 1;
return ERR_NO_ERROR;
}
void AD_init()
{
*(volatile uint16_t*)(ADDR+((1)<<2)) = 1;
EVMOMAPL138_pinmuxConfig(PINMUX_AD_INT_EN_REG, PINMUX_AD_INT_EN_MASK, PINMUX_AD_INT_EN_VAL);
GPIO_setDir(GPIO_BANK2, GPIO_PIN2, GPIO_INPUT);
BINTEN &= ~(1 << GPIO_BANK2); //Disable GP2 Bank Interrupt
CLR_RIS_TRIG23 |= 4; //Disable GP2[2] Rising Edge Interrupt
SET_FAL_TRIG23 |= 4; //Set GP2[2] Falling Edge Interrupt
INTSTAT23 |= 4; //Clear GP2[2] Interrupt State
}
void DMAconfig()
{
struct EDMA3CC_PaRAM *pEDMA3CC_PaRAM;
BINTEN &= ~(1 << GPIO_BANK2); //Disable GP2 Bank Interrupt
INTSTAT23 |= 4; //Clear GP2[2] Interrupt State
EDMA3_0_EECR = 0xffffffff;
EDMA3_0_IECR = 0xffffffff;
EDMA3_0_ICR = 0xffffffff;
EDMA3_0_SECR = 0xffffffff;
EDMA3_0_EMCR = 0xffffffff;
EDMA3_0_ECR = 0xffffffff;
EDMA3_0_DRAE1 = 0xffffffff;
pEDMA3CC_PaRAM = EDMA3_GPIO2;
pEDMA3CC_PaRAM -> OPT = (1 << 20) | (22 << 12) | (1 << 8) | (1 << 2);
pEDMA3CC_PaRAM -> SRC = (volatile uint16_t *)0x64000800;//FIFO_DATA;
pEDMA3CC_PaRAM -> A_B_CNT = (32768 << 16) | 2;
pEDMA3CC_PaRAM -> DST = AD_BUF;
pEDMA3CC_PaRAM -> SRC_DST_BIDX = (2 << 16);
pEDMA3CC_PaRAM -> LINK_BCNTRLD = (32768 << 16) | 0xFFFF;
pEDMA3CC_PaRAM -> SRC_DST_CIDX = 0;
pEDMA3CC_PaRAM -> CCNT = 1;
pEDMA3CC_PaRAM = EDMA3CC_PaRAM127;
pEDMA3CC_PaRAM -> OPT = (1 << 20) | (2 << 12) | (1 << 8) | (1 << 2);
pEDMA3CC_PaRAM -> SRC = (volatile uint16_t *)0x64000800;//FIFO_DATA;
pEDMA3CC_PaRAM -> A_B_CNT = (32768 << 16) | 2;
pEDMA3CC_PaRAM -> DST = AD_BUF;
pEDMA3CC_PaRAM -> SRC_DST_BIDX = (2 << 16);
pEDMA3CC_PaRAM -> LINK_BCNTRLD = (32768 << 16) | 0xFFFF;
pEDMA3CC_PaRAM -> SRC_DST_CIDX = 0;
pEDMA3CC_PaRAM -> CCNT = 1;
EDMA3_0_IESR |= (1 << 22);//GP2 Interrput Enable EDMA
EDMA3_0_EESR |= (1 << 22);
}
