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Hi,
I test UART Rx interrupt work OK, but when i modify the IER register to 0x03, just enable both RX/TX interrupt, but the interrupt not occur again, so i make IER=0x02,just enable Tx interrupt ,but also not work, So, what I need to do?
thansk in advance
Hi Qiang,
Could you provide some more information on your software setup? How do you have the UART setup? Which UART are you using and how are you setup to receive the interrupt?
Thanks,
Casey
Hi,
Here is my serial port initialization procedure:
void UartInit_self(void)
{
UartSetBaudRate_self(9600);
hUartRegs->IER=0x03; //Both TX and RX interrupt enable
hUartRegs->MCR = 0;
hUartRegs->PWREMU_MGMT = 0x6001;
hUartRegs->FCR|=0x01;
hUartRegs->FCR|=0x06;
hUartRegs->FCR&=0xF7;
return;
}
Serial port interrupt configuration is as follows:
void Setup_UART_Interrupt()
{
int eventId;
Hwi_Params params;
Error_Block eb1;
CpIntc_mapSysIntToHostInt(0, SYSTEM_INTERRUPT_UART_A, CIC_HOST_INTERRUPT4UART);
// CpIntc_dispatchPlug(SYSTEM_INTERRUPT_UART_A, &dummy_isr, SYSTEM_INTERRUPT_UART_A, TRUE);
CpIntc_dispatchPlug(SYSTEM_INTERRUPT_UART_A,uart_isr, SYSTEM_INTERRUPT_UART_A, TRUE);
CpIntc_enableHostInt(0, CIC_HOST_INTERRUPT4UART);
/* Enable the System Interrupt 20131201 */
// CpIntc_enableSysInt(0, SYSTEM_INTERRUPT_UART_A);
eventId = CpIntc_getEventId(CIC_HOST_INTERRUPT4UART);
Hwi_Params_init(¶ms);
params.arg = CIC_HOST_INTERRUPT4UART;
params.eventId = eventId;
params.enableInt = TRUE;
// Hwi_create(INTC_INTERRUPT4UART, (ti_sysbios_interfaces_IHwi_FuncPtr)uart_isr, ¶ms, NULL);
Hwi_create(INTC_INTERRUPT4UART, &CpIntc_dispatch, ¶ms, &eb1);
if (Error_check(&eb1)) {
System_printf("Hwi_create() failed!\n");
}
Hwi_enableInterrupt(INTC_INTERRUPT4UART);
} // Setup_UART_Interrupt
when I modify hUartRegs->IER=0x01 ,RX interrupt could happen,but hUartRegs->IER=0x02 or hUartRegs->IER=0x03,both TX and RX interrupt will not work.
Hi Qiang,
Just a few more questions. What do you have SYSTEM_INTERRUPT_UART_A and CIC_HOST_INTERRUPT4UART set as? If the code isn't very large and you don't mind you could just attach it as well and I can take a look at that.
Hi Qiang,
I've recreated the problem on a board I have here but haven't been able to track down the cause. It looks like you have everything setup correctly according to the documentation, at least with regards to the interrupt, but I'll continue to look at it and let you know if I find anything.
Qiang,
I modified your example a little bit to use CSL interrupt setup functions instead of BIOS interrupt setup. Then I could see both TX and RX interrupt events are working (uart_isr_cnt and uart_isr_cnt1 keep counting) when I input some letters in the UART terminal console from PC.
Also please note that FCR is written only that we should not use "|" or "&" operations which depends on the read back value (will read back IIR value).
Please take a look at the modified example below and we need to include the CSL libraries (such as below) in the project as well in order to use the CSL APIs:
"C:\ti\pdk_C6657_1_1_2_6\packages\ti\csl\lib\ti.csl.ae66"
"C:\ti\pdk_C6657_1_1_2_6\packages\ti\csl\lib\ti.csl.intc.ae66"
/*
* ======== main.c ========
*/
#include <cerrno>
#include <string.h>
#include <stdlib.h>
#include <xdc/std.h>
#include <stdio.h>
#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>
//add by michheal 20131126
#include <ti/sysbios/family/c66/tci66xx/CpIntc.h>
#include <ti/sysbios/hal/Hwi.h>
#include "ti/platform/platform.h"
#include <ti/platform/resource_mgr.h>
#include <cslr_uart.h>
#include <evmc665x_uart.h>
#include <ti/csl/src/intc/csl_intc.h>
#include <ti/csl/csl_cpIntcAux.h>
/* Intc variable declarartion */
CSL_CPINTC_Handle handleCIC0;
CSL_CPINTC_Handle handleCIC1;
CSL_IntcContext intcContext;
CSL_IntcEventHandlerRecord EventHandler[30];
CSL_IntcObj intcObj;
CSL_IntcHandle hTest;
CSL_IntcGlobalEnableState state;
CSL_IntcEventHandlerRecord EventRecord;
CSL_IntcParam vectId;
int UartTest(void);
#define CIC_HOST_INTERRUPT4UART 42
#define INTC_INTERRUPT4UART 9
#define SYSTEM_INTERRUPT_UART_A 164
#define SYSTEM_INTERRUPT_UART_B 40
#define UART_FIFO_SIZE 14
#define TX_BUFFER_SIZE 0x1000
#define RX_BUFFER_SIZE 0x1000
#define TX_CIR_BUF_NEXT(x) ((x+1)&(TX_BUFFER_SIZE-1))
#define TX_CIR_BUF_INC(x) (x=(TX_CIR_BUF_NEXT(x)))
#define RX_CIR_BUF_NEXT(x) ((x+1)&(RX_BUFFER_SIZE-1))
#define RX_CIR_BUF_INC(x) (x=(RX_CIR_BUF_NEXT(x)))
#pragma DATA_ALIGN(Tx_Cir_Buf, 32)
Uint8 Tx_Cir_Buf[2][TX_BUFFER_SIZE];
Uint32 Tx_Buf_Head = 0, Tx_Buf_Tail = 0;
#pragma DATA_ALIGN(Rx_Cir_Buf, 32)
Uint8 Rx_Cir_Buf[2][RX_BUFFER_SIZE];
Uint32 Rx_Buf_Head = 0, Rx_Buf_Tail = 0;
Uint32 uart_isr_flag = 0;
Uint32 UART_Error = 0;
Uint32 UART_Receive_Con=0;
Uint32 uart_isr_cnt = 0;
Uint32 uart_isr_cnt1 = 0;
/* Clock rate */
#define PLATFORM_BASE_CLK_RATE_MHZ (100)
/* PREDIV */
#define PLATFORM_PLL_PREDIV_val (1)
/* POSTDIV */
#define PLATFORM_PLL_POSTDIV_val (2)
/* Default PLL PLLM value (100 * 20/(1*2)) = 1.0GHz) */
#define PLATFORM_PLL1_PLLM_val (20)
/* Default PLL PLLD value for 1.0GHz) */
#define PLATFORM_PLL1_PLLD_val (1)
/* Default UART baudrate value */
//#define PLATFORM_UART_BAUDRATE_val (19200)
/* Input crystal frequency 100 MHz */
#define PLATFORM_UART_INPUT_CLOCK_RATE ((PLATFORM_BASE_CLK_RATE_MHZ * PLATFORM_PLL1_PLLM_val * 1000000)/(PLATFORM_PLL_PREDIV_val * 12 * PLATFORM_PLL1_PLLD_val)) /* SYSCLK7 = CPU_CLK/7 in Hz */
void UartSetBaudRate_self(uint32_t baudrate)
{
uint8_t uiDLLVal = 0;
uint8_t uiDLHVal = 0;
Uint16 uiBaudRate=0;
uiBaudRate = ((Uint16) (PLATFORM_UART_INPUT_CLOCK_RATE/(baudrate * 16)));
hUartRegs->LCR = 0x80;
uiDLLVal = (uint8_t )(0x00FF & uiBaudRate);
uiDLHVal = (uint8_t )(0x00FF & (uiBaudRate >> 8));
// Set the baudrate,for accessing LCR[7] should be enable
hUartRegs->DLL = uiDLLVal;
hUartRegs->DLH = uiDLHVal;
hUartRegs->LCR = 0x03;
}
/******************************************************************************
*
* Function: UartInit
*
* Description: This function initializes the UART.
*
* Parameters: void
*
* Return Value: void
*
******************************************************************************/
void UartInit_self(void)
{
//reset UART
hUartRegs->PWREMU_MGMT = 0x0;
/*
// Allows access to the divisor latches of the baud generator during a
// read or write operation (DLL and DLH)
CSL_FINS (hUartRegs->LCR, UART_LCR_DLAB, CSL_UART_LCR_DLAB_ENABLE);
// Break condition is disabled.
CSL_FINS (hUartRegs->LCR, UART_LCR_BC, CSL_UART_LCR_BC_DISABLE);
// Stick parity is disabled.
CSL_FINS (hUartRegs->LCR, UART_LCR_SP, CSL_UART_LCR_SP_DISABLE);
// No PARITY bit is transmitted or checked
CSL_FINS (hUartRegs->LCR, UART_LCR_PEN, CSL_UART_LCR_PEN_DISABLE);
//hUartRegs->LCR = 0x80;
// Set the baudrate,for accessing LCR[7] should be enable
hUartRegs->DLL = DLL_VAL;
hUartRegs->DLH = DLM_VAL;
// Allows access to the receiver buffer register (RBR),
// the transmitter holding register (THR), and the
// interrupt enable register (IER) selected.
CSL_FINS (hUartRegs->LCR, UART_LCR_DLAB, CSL_UART_LCR_DLAB_DISABLE);
// Even Parity is selected
// CSL_FINS (hUartRegs->LCR, UART_LCR_EPS, CSL_UART_LCR_EPS_EVEN);
// Parity Enable
CSL_FINS (hUartRegs->LCR, UART_LCR_PEN, CSL_UART_LCR_PEN_DISABLE);
*/
UartSetBaudRate_self(9600);
/*
// Disable THR, RHR, Receiver line status interrupts
//modify by micheal 20131126
CSL_FINS (hUartRegs->IER, UART_IER_ERBI, CSL_UART_IER_ERBI_DISABLE);
CSL_FINS (hUartRegs->IER, UART_IER_ETBEI, CSL_UART_IER_ETBEI_ENABLE);
CSL_FINS (hUartRegs->IER, UART_IER_ELSI, CSL_UART_IER_ELSI_DISABLE);
CSL_FINS (hUartRegs->IER, UART_IER_EDSSI, CSL_UART_IER_EDSSI_DISABLE);
*/
hUartRegs->IER=0x03;
/* If autoflow control is desired,
* write appropriate values to the modem
* control register (MCR). Note that all UARTs
* do not support autoflow control, see
* the device-specific data manual for supported features.
*
* MCR
* ====================================================
* Bit Field Value Description
* 5 AFE 0 Autoflow control is disabled
* 4 LOOP 0 Loop back mode is disabled.
* 1 RTS 0 RTS control (UARTn_RTS is disabled,
* UARTn_CTS is only enabled.)
* =====================================================
*
*
*/
hUartRegs->MCR = 0;
/* Cleanup previous data (rx trigger is also set to 0)*/
/* Set FCR = 0x07; */
/*
CSL_FINS (hUartRegs->FCR, UART_FCR_FIFOEN, CSL_UART_FCR_FIFOEN_ENABLE);
CSL_FINS (hUartRegs->FCR, UART_FCR_TXCLR, CSL_UART_FCR_TXCLR_CLR);
CSL_FINS (hUartRegs->FCR, UART_FCR_RXCLR, CSL_UART_FCR_RXCLR_CLR);
CSL_FINS (hUartRegs->FCR, UART_FCR_DMAMODE1, CSL_UART_FCR_DMAMODE1_DISABLE);
//modify by mcheal 20131126
CSL_FINS (hUartRegs->FCR, UART_FCR_RXFIFTL, CSL_UART_FCR_RXFIFTL_CHAR1);
*/
//hUartRegs->FCR|=0x01;
//hUartRegs->FCR|=0x06;
//hUartRegs->FCR&=0xF7;
//only write to FCR, not read back
hUartRegs->FCR = 0x7;
/* Choose the desired response to
* emulation suspend events by configuring
* the FREE bit and enable the UART by setting
* the UTRST and URRST bits in the power and
* emulation management register (PWREMU_MGMT).
*
*
* PWREMU_MGMT
* =================================================
* Bit Field Value Description
* 14 UTRST 1 Transmitter is enabled
* 13 URRST 1 Receiver is enabled
* 0 FREE 1 Free-running mode is enabled
* ===================================================
*
*/
hUartRegs->PWREMU_MGMT = 0x6001;
return;
}
void EVM_init()
{
int i;
platform_init_flags sFlags;
platform_init_config sConfig;
/* Status of the call to initialize the platform */
Int32 pform_status;
/* Platform Information - we will read it form the Platform Library */
platform_info sPlatformInfo;
/*
* You can choose what to initialize on the platform by setting the following
* flags. We will initialize everything.
*/
memset( (void *) &sFlags, 0, sizeof(platform_init_flags));
memset( (void *) &sConfig, 0, sizeof(platform_init_config));
sFlags.pll = 0;
sFlags.ddr = 0;
sFlags.tcsl = 0; /* Time stamp counter */
sFlags.phy = 0; /* Ethernet */
sFlags.ecc = 0;
sConfig.pllm = 0;
pform_status = platform_init(&sFlags, &sConfig);
/* If we initialized the platform okay */
if (pform_status == Platform_EOK) {
/* Get information about the platform so we can use it in various places */
memset( (void *) &sPlatformInfo, 0, sizeof(platform_info));
(void) platform_get_info(&sPlatformInfo);
}
else {
/* Intiialization of the platform failed... die */
printf("Platform failed to initialize. Error code %d \n", pform_status);
printf("We will die in an infinite loop... \n");
while (1) {
(void) platform_led(1, PLATFORM_LED_ON, (LED_CLASS_E) PLATFORM_USER_LED_CLASS);
(void) platform_delay(50000);
(void) platform_led(1, PLATFORM_LED_OFF, (LED_CLASS_E) PLATFORM_USER_LED_CLASS);
(void) platform_delay(50000);
};
}
platform_write_configure(PLATFORM_WRITE_PRINTF);
// platform_uart_init();
UartInit_self();
UartSetBaudRate_self(9600);
// platform_uart_set_baudrate(9600);
/* Check to see that we are running on the Master Core */
if (platform_get_coreid() != 0) {
/* We are not on the Master Core... die */
printf("You must run this application on Core 0. \n");
printf("We will die in an infinite loop... \n");
while (1) {
(void) platform_led(1, PLATFORM_LED_ON, (LED_CLASS_E) PLATFORM_USER_LED_CLASS);
(void) platform_delay(50000);
(void) platform_led(1, PLATFORM_LED_OFF, (LED_CLASS_E) PLATFORM_USER_LED_CLASS);
(void) platform_delay(50000);
};
}
/* Clear the state of the LEDs to OFF */
for (i=0; i < sPlatformInfo.led[1].count; i++) {
platform_led(i, PLATFORM_LED_OFF, (LED_CLASS_E) PLATFORM_USER_LED_CLASS);
}
return;
}
/******************************************************************************/
// write data from Tx circular buffer to UART0 port. Tail chase head,
// called from idle task.
/******************************************************************************/
void Write_UART()
{
Uint8 ch;
Uint32 i;
Uint32 int_id;
if (CSL_UART_LSR_THRE_FULL == (CSL_FEXT(hUartRegs->LSR, UART_LSR_THRE)))
return;
// int_id = CSL_FEXT(hUartRegs->IIR, UART_IIR_INTID);
// System_printf("int_id:%d\n",int_id);
for (i = 0; i < UART_FIFO_SIZE; i++)
{
if (Tx_Buf_Tail == Tx_Buf_Head)
break; // no more to write.
ch = Tx_Cir_Buf[0][Tx_Buf_Tail];
CSL_FINS(hUartRegs->THR, UART_THR_DATA, ch);
#ifdef UART_SYSTEM_TEST
if (ch == 0x0D)
CSL_FINS(hUartRegs->THR, UART_THR_DATA, 0x0A);
#endif
TX_CIR_BUF_INC(Tx_Buf_Tail);
}
//test and verify if the ETBEI and ERBI is chenged
while(1){
int_id= CSL_FEXT(hUartRegs->IIR, UART_IIR_INTID);
if(int_id != 0)
{
System_printf("LSR:%d\n",hUartRegs->LSR);
System_printf("UART_IER_ETBEI:%d\n", CSL_FEXT(hUartRegs->IER, UART_IER_ETBEI));
System_printf("UART_IER_ERBI:%d\n", CSL_FEXT(hUartRegs->IER, UART_IER_ERBI));
System_printf("UART_LSR_THRE:%d\n", CSL_FEXT(hUartRegs->LSR, UART_LSR_THRE));
System_printf("int_id:%d\n",int_id);
break;
}
}
} // Write_UART
/******************************************************************************/
// read data from UART0 port to rx circular buffer. Head chase tail, but
// cannot equal to tail. Called from isr.
/******************************************************************************/
void Read_UART()
{
Uint8 ch;
while (CSL_UART_LSR_DR_READY == (CSL_FEXT(hUartRegs->LSR, UART_LSR_DR)))
{
if (RX_CIR_BUF_NEXT(Rx_Buf_Head) == Rx_Buf_Tail)
{
UART_Error++;
// LOGSTATUS(UART_INPUT_OVERRUN);
break;
}
ch = CSL_FEXT(hUartRegs->RBR, UART_RBR_DATA);
Rx_Cir_Buf[0][Rx_Buf_Head] = ch;
RX_CIR_BUF_INC(Rx_Buf_Head);
}
} // Read_UART
/******************************************************************************/
// application writes output data to UART tx circular buffer. Head chase tail,
// but cannot equal to tail.
// return: number of bytes wrote.
/******************************************************************************/
Uint32 UART_Output(Int8 buf[], Uint32 size)
{
Uint32 i;
for (i = 0; i < size; i++)
{
if (TX_CIR_BUF_NEXT(Tx_Buf_Head) == Tx_Buf_Tail)
{
// LOGSTATUS(UART_OUTPUT_OVERRUN);
break; // buffer over flow
}
Tx_Cir_Buf[0][Tx_Buf_Head] = buf[i];
TX_CIR_BUF_INC(Tx_Buf_Head);
}
return i;
} // UART_Output
/******************************************************************************/
// Application reads input data from UART rx circular buffer. Tail chase head.
// return: number of bytes read.
/******************************************************************************/
Uint32 UART_Input(Int8 buf[], Uint32 size)
{
Uint32 i;
for (i = 0; i < size; i++)
{
if (Rx_Buf_Tail == Rx_Buf_Head)
break; // no more data
buf[i] = Rx_Cir_Buf[0][Rx_Buf_Tail];
#ifdef UART_SYSTEM_TEST
CSL_FINS(hUartRegs->THR, UART_THR_DATA, buf[i]);
if (buf[i] == 0x0D)
CSL_FINS(hUartRegs->THR, UART_THR_DATA, 0x0A);
#endif
RX_CIR_BUF_INC(Rx_Buf_Tail);
}
return i;
} // UART_Input
/*
* ======== taskFxn ========
*/
Void taskFxn(UArg a0, UArg a1)
{
int8_t buf[200]={0};
uint32_t len=0;
uint32_t i=0;
System_printf("enter taskFxn()\n");
// System_printf("hUartRegs->IER:%d\n",hUartRegs->IER);
// System_printf("hUartRegs->FCR:%d\n",hUartRegs->FCR);
UartTest();
Write_UART();
while(1){
len=UART_Input(buf,50);
if(len>0){
System_printf("Len:%d\n",len);
UART_Receive_Con+=len;
System_printf("uart_isr_cnt:%d\n",uart_isr_cnt);
System_printf("uart_isr_cnt1:%d\n",uart_isr_cnt1);
for(i=0;i<len;i++)
{
System_printf("%c",buf[i]);
System_printf("\n");
}
UART_Output(buf, len);
Write_UART();
}
}
// System_printf("exit taskFxn()\n");
}
/*
ti_sysbios_interfaces_IHwi_FuncPtr uart_isr (UArg arg)
{
Uint32 int_id;
// uart_isr_flag++;
uart_isr_cnt++;
CpIntc_disableHostInt(0, CIC_HOST_INTERRUPT4UART);
CpIntc_clearSysInt(0, SYSTEM_INTERRUPT_UART_A);
int_id = CSL_FEXT(hUartRegs->IIR, UART_IIR_INTID);
switch (int_id)
{
case CSL_UART_IIR_INTID_MODSTAT:
break;
case CSL_UART_IIR_INTID_THRE:
Write_UART();
break;
case CSL_UART_IIR_INTID_RDA:
case CSL_UART_IIR_INTID_CTI:
uart_isr_cnt1++;
Read_UART();
#ifdef UART_SYSTEM_TEST
UART_Input(UART_Test_Buf, sizeof(UART_Test_Buf));
#endif
break;
case CSL_UART_IIR_INTID_RLS:
break;
default: // reserved
break;
}
Hwi_clearInterrupt(INTC_INTERRUPT4UART);
CpIntc_enableHostInt(0, CIC_HOST_INTERRUPT4UART);
return NULL;
}
*/
//ti_sysbios_interfaces_IHwi_FuncPtr
void uart_isr (UArg arg)
{
Uint32 int_id;
// uart_isr_flag++;
uart_isr_cnt++;
CpIntc_disableHostInt(0, CIC_HOST_INTERRUPT4UART);
CpIntc_clearSysInt(0, SYSTEM_INTERRUPT_UART_A);
int_id = CSL_FEXT(hUartRegs->IIR, UART_IIR_INTID);
switch (int_id)
{
case CSL_UART_IIR_INTID_MODSTAT:
break;
case CSL_UART_IIR_INTID_THRE:
Write_UART();
break;
case CSL_UART_IIR_INTID_RDA:
case CSL_UART_IIR_INTID_CTI:
uart_isr_cnt1++;
Read_UART();
#ifdef UART_SYSTEM_TEST
UART_Input(UART_Test_Buf, sizeof(UART_Test_Buf));
#endif
break;
case CSL_UART_IIR_INTID_RLS:
break;
default: // reserved
break;
}
Hwi_clearInterrupt(INTC_INTERRUPT4UART);
CpIntc_enableHostInt(0, CIC_HOST_INTERRUPT4UART);
// return NULL;
}
/*
* ======== main ========
*/
#if 0
void Setup_UART_Interrupt()
{
int eventId;
Hwi_Params params;
Error_Block eb1;
CpIntc_mapSysIntToHostInt(0, SYSTEM_INTERRUPT_UART_A, CIC_HOST_INTERRUPT4UART);
// CpIntc_dispatchPlug(SYSTEM_INTERRUPT_UART_A, &dummy_isr, SYSTEM_INTERRUPT_UART_A, TRUE);
//CpIntc_dispatchPlug(SYSTEM_INTERRUPT_UART_A,uart_isr, SYSTEM_INTERRUPT_UART_A, TRUE);
CpIntc_dispatchPlug(SYSTEM_INTERRUPT_UART_A,uart_isr, SYSTEM_INTERRUPT_UART_A, TRUE);
CpIntc_enableHostInt(0, CIC_HOST_INTERRUPT4UART);
/* Enable the System Interrupt 20131201 */
CpIntc_enableSysInt(0, SYSTEM_INTERRUPT_UART_A);
eventId = CpIntc_getEventId(CIC_HOST_INTERRUPT4UART);
Hwi_Params_init(¶ms);
params.arg = CIC_HOST_INTERRUPT4UART;
params.eventId = eventId;
params.enableInt = TRUE;
// Hwi_create(INTC_INTERRUPT4UART, (ti_sysbios_interfaces_IHwi_FuncPtr)uart_isr, ¶ms, NULL);
//Hwi_create(INTC_INTERRUPT4UART, &CpIntc_dispatch, ¶ms, &eb1);
Hwi_create(INTC_INTERRUPT4UART, uart_isr, ¶ms, &eb1);
if (Error_check(&eb1)) {
System_printf("Hwi_create() failed!\n");
}
Hwi_enableInterrupt(INTC_INTERRUPT4UART);
} // Setup_UART_Interrupt
#endif
CSL_CPINTC_Handle InitializeCPINTC(unsigned int aCICNumber)
{
CSL_CPINTC_Handle localHandleCIC;
/* Open the handle to the CPINT Instance */
localHandleCIC = CSL_CPINTC_open(aCICNumber);
if (localHandleCIC == 0)
{
printf ("Error: Unable to open CPINTC: %d\n", aCICNumber);
return NULL;
}
/* Disable all host interrupts. */
CSL_CPINTC_disableAllHostInterrupt(localHandleCIC);
/* Configure no nesting support in the CPINTC Module. */
CSL_CPINTC_setNestingMode (localHandleCIC, CPINTC_NO_NESTING);
/*map system event to host output*/
CSL_CPINTC_mapSystemIntrToChannel (localHandleCIC, SYSTEM_INTERRUPT_UART_A, CIC_HOST_INTERRUPT4UART);
/* enable system event*/
CSL_CPINTC_enableSysInterrupt (localHandleCIC, SYSTEM_INTERRUPT_UART_A);
/* enable host output*/
CSL_CPINTC_enableHostInterrupt (localHandleCIC, CIC_HOST_INTERRUPT4UART);
/* Enable all host interrupts also. */
CSL_CPINTC_enableAllHostInterrupt(localHandleCIC);
return localHandleCIC;
}
int Setup_UART_Interrupt()
{
/* INTC module initialization */
intcContext.numEvtEntries = 10;
intcContext.eventhandlerRecord = EventHandler;
if (CSL_intcInit(&intcContext) != CSL_SOK)
{
printf("Error: GEM-INTC initialization failed\n");
return 0;
}
/* Enable NMIs */
if (CSL_intcGlobalNmiEnable() != CSL_SOK)
{
printf("Error: GEM-INTC global NMI enable failed\n");
return 0;
}
/* Enable global interrupts */
if (CSL_intcGlobalEnable(&state) != CSL_SOK)
{
printf ("Error: GEM-INTC global enable failed\n");
return 0;
}
/* Open the INTC Module for Vector ID: 5 and Event ID: 58
* Refer to the interrupt architecture and mapping document for the Event ID CIC0_OUT(42)*/
vectId = CSL_INTC_VECTID_5;
hTest = CSL_intcOpen (&intcObj, 58, &vectId, NULL);
if (hTest == NULL)
{
printf("Error: GEM-INTC Open failed\n");
return 0;
}
/* Register an call-back handler which is invoked when the event occurs. */
EventRecord.handler = (CSL_IntcEventHandler)&uart_isr;
EventRecord.arg = 0;
if (CSL_intcPlugEventHandler(hTest,&EventRecord) != CSL_SOK)
{
printf("Error: GEM-INTC Plug event handler failed\n");
return 0;
}
/* Enabling the events. */
if (CSL_intcHwControl(hTest,CSL_INTC_CMD_EVTENABLE, NULL) != CSL_SOK)
{
printf("Error: GEM-INTC CSL_INTC_CMD_EVTENABLE command failed\n");
return 0;
}
//IlkleCoreLevelInterruptController(&edma3_isr_handler, EDMA3CC2EVENT_ID_INT, CSL_INTC_VECTID_5);
handleCIC0 = InitializeCPINTC(0); //initialize cpintc0
if (handleCIC0 == 0)
{
printf ("Error: Unable to open CPINTC0\n");
return 0;
}
}
Void main()
{
Task_Handle task;
Error_Block eb;
Setup_UART_Interrupt();
UartInit_self();
//UartSetBaudRate_self(9600);
// platform_uart_set_baudrate(9600);
//Setup_UART_Interrupt();
// Hwi_enable();
Error_init(&eb);
task = Task_create(taskFxn, NULL, &eb);
if (task == NULL) {
System_printf("Task_create() failed!\n");
BIOS_exit(0);
}
BIOS_start(); /* enable interrupts and start SYS/BIOS */
}
int UartTest()
{
int8_t message[] = "\r\n123456789012345678901234567890123456789012345678901234567890\r\n";
int length = strlen((char *)message);
UART_Output(message, length);
return(0);
}
Qiang,
I think we can still use BIOS setup but we need to initialize CorePac INTC first (make CorePac ready to receive system interrupt) and then initialize CIC (CPINTC) interrupt (enable system interrupt).
Please take a look at the following example using BIOS and I also removed some "printf" to resolve BIOS complaining.
Hope it is what you expect.
/*
* ======== main.c ========
*/
#include <cerrno>
#include <string.h>
#include <stdlib.h>
#include <xdc/std.h>
#include <stdio.h>
#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>
//add by michheal 20131126
#include <ti/sysbios/family/c66/tci66xx/CpIntc.h>
#include <ti/sysbios/hal/Hwi.h>
#include "ti/platform/platform.h"
#include <ti/platform/resource_mgr.h>
#include <cslr_uart.h>
#include <evmc665x_uart.h>
#include <ti/csl/src/intc/csl_intc.h>
#include <ti/csl/csl_cpIntcAux.h>
int UartTest(void);
#define CIC_HOST_INTERRUPT4UART 42
#define INTC_INTERRUPT4UART 9
#define SYSTEM_INTERRUPT_UART_A 164
#define SYSTEM_INTERRUPT_UART_B 40
#define UART_FIFO_SIZE 14
#define TX_BUFFER_SIZE 0x1000
#define RX_BUFFER_SIZE 0x1000
#define TX_CIR_BUF_NEXT(x) ((x+1)&(TX_BUFFER_SIZE-1))
#define TX_CIR_BUF_INC(x) (x=(TX_CIR_BUF_NEXT(x)))
#define RX_CIR_BUF_NEXT(x) ((x+1)&(RX_BUFFER_SIZE-1))
#define RX_CIR_BUF_INC(x) (x=(RX_CIR_BUF_NEXT(x)))
#pragma DATA_ALIGN(Tx_Cir_Buf, 32)
Uint8 Tx_Cir_Buf[2][TX_BUFFER_SIZE];
Uint32 Tx_Buf_Head = 0, Tx_Buf_Tail = 0;
#pragma DATA_ALIGN(Rx_Cir_Buf, 32)
Uint8 Rx_Cir_Buf[2][RX_BUFFER_SIZE];
Uint32 Rx_Buf_Head = 0, Rx_Buf_Tail = 0;
Uint32 uart_isr_flag = 0;
Uint32 UART_Error = 0;
Uint32 UART_Receive_Con=0;
Uint32 uart_isr_cnt = 0;
Uint32 uart_isr_cnt1 = 0;
CSL_CPINTC_Handle handleCIC0;
CSL_CPINTC_Handle handleCIC1;
CSL_IntcContext intcContext;
CSL_IntcEventHandlerRecord EventHandler[30];
CSL_IntcObj intcObj;
CSL_IntcHandle hTest;
CSL_IntcGlobalEnableState state;
CSL_IntcEventHandlerRecord EventRecord;
CSL_IntcParam vectId;
/* Clock rate */
#define PLATFORM_BASE_CLK_RATE_MHZ (100)
/* PREDIV */
#define PLATFORM_PLL_PREDIV_val (1)
/* POSTDIV */
#define PLATFORM_PLL_POSTDIV_val (2)
/* Default PLL PLLM value (100 * 20/(1*2)) = 1.0GHz) */
#define PLATFORM_PLL1_PLLM_val (20)
/* Default PLL PLLD value for 1.0GHz) */
#define PLATFORM_PLL1_PLLD_val (1)
/* Default UART baudrate value */
//#define PLATFORM_UART_BAUDRATE_val (19200)
/* Input crystal frequency 100 MHz */
#define PLATFORM_UART_INPUT_CLOCK_RATE ((PLATFORM_BASE_CLK_RATE_MHZ * PLATFORM_PLL1_PLLM_val * 1000000)/(PLATFORM_PLL_PREDIV_val * 12 * PLATFORM_PLL1_PLLD_val)) /* SYSCLK7 = CPU_CLK/7 in Hz */
void UartSetBaudRate_self(uint32_t baudrate)
{
uint8_t uiDLLVal = 0;
uint8_t uiDLHVal = 0;
Uint16 uiBaudRate=0;
uiBaudRate = ((Uint16) (PLATFORM_UART_INPUT_CLOCK_RATE/(baudrate * 16)));
hUartRegs->LCR = 0x80;
uiDLLVal = (uint8_t )(0x00FF & uiBaudRate);
uiDLHVal = (uint8_t )(0x00FF & (uiBaudRate >> 8));
// Set the baudrate,for accessing LCR[7] should be enable
hUartRegs->DLL = uiDLLVal;
hUartRegs->DLH = uiDLHVal;
hUartRegs->LCR = 0x03;
}
/******************************************************************************
*
* Function: UartInit
*
* Description: This function initializes the UART.
*
* Parameters: void
*
* Return Value: void
*
******************************************************************************/
void UartInit_self(void)
{
//reset UART
hUartRegs->PWREMU_MGMT = 0x0;
/*
// Allows access to the divisor latches of the baud generator during a
// read or write operation (DLL and DLH)
CSL_FINS (hUartRegs->LCR, UART_LCR_DLAB, CSL_UART_LCR_DLAB_ENABLE);
// Break condition is disabled.
CSL_FINS (hUartRegs->LCR, UART_LCR_BC, CSL_UART_LCR_BC_DISABLE);
// Stick parity is disabled.
CSL_FINS (hUartRegs->LCR, UART_LCR_SP, CSL_UART_LCR_SP_DISABLE);
// No PARITY bit is transmitted or checked
CSL_FINS (hUartRegs->LCR, UART_LCR_PEN, CSL_UART_LCR_PEN_DISABLE);
//hUartRegs->LCR = 0x80;
// Set the baudrate,for accessing LCR[7] should be enable
hUartRegs->DLL = DLL_VAL;
hUartRegs->DLH = DLM_VAL;
// Allows access to the receiver buffer register (RBR),
// the transmitter holding register (THR), and the
// interrupt enable register (IER) selected.
CSL_FINS (hUartRegs->LCR, UART_LCR_DLAB, CSL_UART_LCR_DLAB_DISABLE);
// Even Parity is selected
// CSL_FINS (hUartRegs->LCR, UART_LCR_EPS, CSL_UART_LCR_EPS_EVEN);
// Parity Enable
CSL_FINS (hUartRegs->LCR, UART_LCR_PEN, CSL_UART_LCR_PEN_DISABLE);
*/
UartSetBaudRate_self(9600);
/*
// Disable THR, RHR, Receiver line status interrupts
//modify by micheal 20131126
CSL_FINS (hUartRegs->IER, UART_IER_ERBI, CSL_UART_IER_ERBI_DISABLE);
CSL_FINS (hUartRegs->IER, UART_IER_ETBEI, CSL_UART_IER_ETBEI_ENABLE);
CSL_FINS (hUartRegs->IER, UART_IER_ELSI, CSL_UART_IER_ELSI_DISABLE);
CSL_FINS (hUartRegs->IER, UART_IER_EDSSI, CSL_UART_IER_EDSSI_DISABLE);
*/
//hUartRegs->IER=0x03;
hUartRegs->IER=0x03;
/* If autoflow control is desired,
* write appropriate values to the modem
* control register (MCR). Note that all UARTs
* do not support autoflow control, see
* the device-specific data manual for supported features.
*
* MCR
* ====================================================
* Bit Field Value Description
* 5 AFE 0 Autoflow control is disabled
* 4 LOOP 0 Loop back mode is disabled.
* 1 RTS 0 RTS control (UARTn_RTS is disabled,
* UARTn_CTS is only enabled.)
* =====================================================
*
*
*/
hUartRegs->MCR = 0;
/* Cleanup previous data (rx trigger is also set to 0)*/
/* Set FCR = 0x07; */
/*
CSL_FINS (hUartRegs->FCR, UART_FCR_FIFOEN, CSL_UART_FCR_FIFOEN_ENABLE);
CSL_FINS (hUartRegs->FCR, UART_FCR_TXCLR, CSL_UART_FCR_TXCLR_CLR);
CSL_FINS (hUartRegs->FCR, UART_FCR_RXCLR, CSL_UART_FCR_RXCLR_CLR);
CSL_FINS (hUartRegs->FCR, UART_FCR_DMAMODE1, CSL_UART_FCR_DMAMODE1_DISABLE);
//modify by mcheal 20131126
CSL_FINS (hUartRegs->FCR, UART_FCR_RXFIFTL, CSL_UART_FCR_RXFIFTL_CHAR1);
*/
//hUartRegs->FCR|=0x01;
//hUartRegs->FCR|=0x06;
//hUartRegs->FCR&=0xF7;
//only write to FCR, not read back
hUartRegs->FCR = 0x7;
/* Choose the desired response to
* emulation suspend events by configuring
* the FREE bit and enable the UART by setting
* the UTRST and URRST bits in the power and
* emulation management register (PWREMU_MGMT).
*
*
* PWREMU_MGMT
* =================================================
* Bit Field Value Description
* 14 UTRST 1 Transmitter is enabled
* 13 URRST 1 Receiver is enabled
* 0 FREE 1 Free-running mode is enabled
* ===================================================
*
*/
hUartRegs->PWREMU_MGMT = 0x6001;
return;
}
void EVM_init()
{
int i;
platform_init_flags sFlags;
platform_init_config sConfig;
/* Status of the call to initialize the platform */
Int32 pform_status;
/* Platform Information - we will read it form the Platform Library */
platform_info sPlatformInfo;
/*
* You can choose what to initialize on the platform by setting the following
* flags. We will initialize everything.
*/
memset( (void *) &sFlags, 0, sizeof(platform_init_flags));
memset( (void *) &sConfig, 0, sizeof(platform_init_config));
sFlags.pll = 0;
sFlags.ddr = 0;
sFlags.tcsl = 0; /* Time stamp counter */
sFlags.phy = 0; /* Ethernet */
sFlags.ecc = 0;
sConfig.pllm = 0;
pform_status = platform_init(&sFlags, &sConfig);
/* If we initialized the platform okay */
if (pform_status == Platform_EOK) {
/* Get information about the platform so we can use it in various places */
memset( (void *) &sPlatformInfo, 0, sizeof(platform_info));
(void) platform_get_info(&sPlatformInfo);
}
else {
/* Intiialization of the platform failed... die */
printf("Platform failed to initialize. Error code %d \n", pform_status);
printf("We will die in an infinite loop... \n");
while (1) {
(void) platform_led(1, PLATFORM_LED_ON, (LED_CLASS_E) PLATFORM_USER_LED_CLASS);
(void) platform_delay(50000);
(void) platform_led(1, PLATFORM_LED_OFF, (LED_CLASS_E) PLATFORM_USER_LED_CLASS);
(void) platform_delay(50000);
};
}
platform_write_configure(PLATFORM_WRITE_PRINTF);
// platform_uart_init();
UartInit_self();
UartSetBaudRate_self(9600);
// platform_uart_set_baudrate(9600);
/* Check to see that we are running on the Master Core */
if (platform_get_coreid() != 0) {
/* We are not on the Master Core... die */
printf("You must run this application on Core 0. \n");
printf("We will die in an infinite loop... \n");
while (1) {
(void) platform_led(1, PLATFORM_LED_ON, (LED_CLASS_E) PLATFORM_USER_LED_CLASS);
(void) platform_delay(50000);
(void) platform_led(1, PLATFORM_LED_OFF, (LED_CLASS_E) PLATFORM_USER_LED_CLASS);
(void) platform_delay(50000);
};
}
/* Clear the state of the LEDs to OFF */
for (i=0; i < sPlatformInfo.led[1].count; i++) {
platform_led(i, PLATFORM_LED_OFF, (LED_CLASS_E) PLATFORM_USER_LED_CLASS);
}
return;
}
/******************************************************************************/
// write data from Tx circular buffer to UART0 port. Tail chase head,
// called from idle task.
/******************************************************************************/
void Write_UART()
{
Uint8 ch;
Uint32 i;
Uint32 int_id;
if (CSL_UART_LSR_THRE_FULL == (CSL_FEXT(hUartRegs->LSR, UART_LSR_THRE)))
return;
// int_id = CSL_FEXT(hUartRegs->IIR, UART_IIR_INTID);
// System_printf("int_id:%d\n",int_id);
for (i = 0; i < UART_FIFO_SIZE; i++)
{
if (Tx_Buf_Tail == Tx_Buf_Head)
break; // no more to write.
ch = Tx_Cir_Buf[0][Tx_Buf_Tail];
CSL_FINS(hUartRegs->THR, UART_THR_DATA, ch);
#ifdef UART_SYSTEM_TEST
if (ch == 0x0D)
CSL_FINS(hUartRegs->THR, UART_THR_DATA, 0x0A);
#endif
TX_CIR_BUF_INC(Tx_Buf_Tail);
}
//test and verify if the ETBEI and ERBI is chenged
while(1){
int_id= CSL_FEXT(hUartRegs->IIR, UART_IIR_INTID);
if(int_id != 0)
{
#if 0
System_printf("LSR:%d\n",hUartRegs->LSR);
System_printf("UART_IER_ETBEI:%d\n", CSL_FEXT(hUartRegs->IER, UART_IER_ETBEI));
System_printf("UART_IER_ERBI:%d\n", CSL_FEXT(hUartRegs->IER, UART_IER_ERBI));
System_printf("UART_LSR_THRE:%d\n", CSL_FEXT(hUartRegs->LSR, UART_LSR_THRE));
System_printf("int_id:%d\n",int_id);
System_printf("IIR is 0x%x\n", hUartRegs->IIR);
#endif
break;
}
}
} // Write_UART
/******************************************************************************/
// read data from UART0 port to rx circular buffer. Head chase tail, but
// cannot equal to tail. Called from isr.
/******************************************************************************/
void Read_UART()
{
Uint8 ch;
while (CSL_UART_LSR_DR_READY == (CSL_FEXT(hUartRegs->LSR, UART_LSR_DR)))
{
if (RX_CIR_BUF_NEXT(Rx_Buf_Head) == Rx_Buf_Tail)
{
UART_Error++;
// LOGSTATUS(UART_INPUT_OVERRUN);
break;
}
ch = CSL_FEXT(hUartRegs->RBR, UART_RBR_DATA);
Rx_Cir_Buf[0][Rx_Buf_Head] = ch;
RX_CIR_BUF_INC(Rx_Buf_Head);
}
} // Read_UART
/******************************************************************************/
// application writes output data to UART tx circular buffer. Head chase tail,
// but cannot equal to tail.
// return: number of bytes wrote.
/******************************************************************************/
Uint32 UART_Output(Int8 buf[], Uint32 size)
{
Uint32 i;
for (i = 0; i < size; i++)
{
if (TX_CIR_BUF_NEXT(Tx_Buf_Head) == Tx_Buf_Tail)
{
// LOGSTATUS(UART_OUTPUT_OVERRUN);
break; // buffer over flow
}
Tx_Cir_Buf[0][Tx_Buf_Head] = buf[i];
TX_CIR_BUF_INC(Tx_Buf_Head);
}
return i;
} // UART_Output
/******************************************************************************/
// Application reads input data from UART rx circular buffer. Tail chase head.
// return: number of bytes read.
/******************************************************************************/
Uint32 UART_Input(Int8 buf[], Uint32 size)
{
Uint32 i;
for (i = 0; i < size; i++)
{
if (Rx_Buf_Tail == Rx_Buf_Head)
break; // no more data
buf[i] = Rx_Cir_Buf[0][Rx_Buf_Tail];
#ifdef UART_SYSTEM_TEST
CSL_FINS(hUartRegs->THR, UART_THR_DATA, buf[i]);
if (buf[i] == 0x0D)
CSL_FINS(hUartRegs->THR, UART_THR_DATA, 0x0A);
#endif
RX_CIR_BUF_INC(Rx_Buf_Tail);
}
return i;
} // UART_Input
/*
* ======== taskFxn ========
*/
Void taskFxn(UArg a0, UArg a1)
{
int8_t buf[200]={0};
uint32_t len=0;
uint32_t i=0;
//System_printf("enter taskFxn()\n");
// System_printf("hUartRegs->IER:%d\n",hUartRegs->IER);
// System_printf("hUartRegs->FCR:%d\n",hUartRegs->FCR);
UartTest();
Write_UART();
while(1){
len=UART_Input(buf,50);
if(len>0){
System_printf("Len:%d\n",len);
UART_Receive_Con+=len;
System_printf("uart_isr_cnt:%d\n",uart_isr_cnt);
System_printf("uart_isr_cnt1:%d\n",uart_isr_cnt1);
for(i=0;i<len;i++)
{
System_printf("%c",buf[i]);
System_printf("\n");
}
UART_Output(buf, len);
Write_UART();
}
}
// System_printf("exit taskFxn()\n");
}
/*
ti_sysbios_interfaces_IHwi_FuncPtr uart_isr (UArg arg)
{
Uint32 int_id;
// uart_isr_flag++;
uart_isr_cnt++;
CpIntc_disableHostInt(0, CIC_HOST_INTERRUPT4UART);
CpIntc_clearSysInt(0, SYSTEM_INTERRUPT_UART_A);
int_id = CSL_FEXT(hUartRegs->IIR, UART_IIR_INTID);
switch (int_id)
{
case CSL_UART_IIR_INTID_MODSTAT:
break;
case CSL_UART_IIR_INTID_THRE:
Write_UART();
break;
case CSL_UART_IIR_INTID_RDA:
case CSL_UART_IIR_INTID_CTI:
uart_isr_cnt1++;
Read_UART();
#ifdef UART_SYSTEM_TEST
UART_Input(UART_Test_Buf, sizeof(UART_Test_Buf));
#endif
break;
case CSL_UART_IIR_INTID_RLS:
break;
default: // reserved
break;
}
Hwi_clearInterrupt(INTC_INTERRUPT4UART);
CpIntc_enableHostInt(0, CIC_HOST_INTERRUPT4UART);
return NULL;
}
*/
//ti_sysbios_interfaces_IHwi_FuncPtr
void uart_isr (UArg arg)
{
Uint32 int_id;
//System_printf ("enter isr\n");
// uart_isr_flag++;
uart_isr_cnt++;
CpIntc_disableHostInt(0, CIC_HOST_INTERRUPT4UART);
CpIntc_clearSysInt(0, SYSTEM_INTERRUPT_UART_A);
int_id = CSL_FEXT(hUartRegs->IIR, UART_IIR_INTID);
switch (int_id)
{
case CSL_UART_IIR_INTID_MODSTAT:
break;
case CSL_UART_IIR_INTID_THRE:
Write_UART();
break;
case CSL_UART_IIR_INTID_RDA:
case CSL_UART_IIR_INTID_CTI:
uart_isr_cnt1++;
Read_UART();
#ifdef UART_SYSTEM_TEST
UART_Input(UART_Test_Buf, sizeof(UART_Test_Buf));
#endif
break;
case CSL_UART_IIR_INTID_RLS:
break;
default: // reserved
break;
}
Hwi_clearInterrupt(INTC_INTERRUPT4UART);
CpIntc_enableHostInt(0, CIC_HOST_INTERRUPT4UART);
// return NULL;
}
/*
* ======== main ========
*/
CSL_CPINTC_Handle InitializeCPINTC(unsigned int aCICNumber)
{
CSL_CPINTC_Handle localHandleCIC;
/* Open the handle to the CPINT Instance */
localHandleCIC = CSL_CPINTC_open(aCICNumber);
if (localHandleCIC == 0)
{
printf ("Error: Unable to open CPINTC: %d\n", aCICNumber);
return NULL;
}
/* Disable all host interrupts. */
CSL_CPINTC_disableAllHostInterrupt(localHandleCIC);
/* Configure no nesting support in the CPINTC Module. */
CSL_CPINTC_setNestingMode (localHandleCIC, CPINTC_NO_NESTING);
/*map system event to host output*/
CSL_CPINTC_mapSystemIntrToChannel (localHandleCIC, SYSTEM_INTERRUPT_UART_A, CIC_HOST_INTERRUPT4UART);
/* enable system event*/
CSL_CPINTC_enableSysInterrupt (localHandleCIC, SYSTEM_INTERRUPT_UART_A);
/* enable host output*/
CSL_CPINTC_enableHostInterrupt (localHandleCIC, CIC_HOST_INTERRUPT4UART);
/* Enable all host interrupts also. */
CSL_CPINTC_enableAllHostInterrupt(localHandleCIC);
return localHandleCIC;
}
void Setup_UART_Interrupt()
{
int eventId;
Hwi_Params params;
Error_Block eb1;
#if 0
/* INTC module initialization */
intcContext.numEvtEntries = 10;
intcContext.eventhandlerRecord = EventHandler;
if (CSL_intcInit(&intcContext) != CSL_SOK)
{
printf("Error: GEM-INTC initialization failed\n");
}
/* Enable NMIs */
if (CSL_intcGlobalNmiEnable() != CSL_SOK)
{
printf("Error: GEM-INTC global NMI enable failed\n");
}
/* Enable global interrupts */
if (CSL_intcGlobalEnable(&state) != CSL_SOK)
{
printf ("Error: GEM-INTC global enable failed\n");
}
/* Open the INTC Module for Vector ID: 5 and Event ID: 58
* Refer to the interrupt architecture and mapping document for the Event ID CIC0_OUT(42)*/
vectId = CSL_INTC_VECTID_5;
hTest = CSL_intcOpen (&intcObj, 58, &vectId, NULL);
if (hTest == NULL)
{
printf("Error: GEM-INTC Open failed\n");
}
/* Register an call-back handler which is invoked when the event occurs. */
EventRecord.handler = (CSL_IntcEventHandler)&uart_isr;
EventRecord.arg = 0;
if (CSL_intcPlugEventHandler(hTest,&EventRecord) != CSL_SOK)
{
printf("Error: GEM-INTC Plug event handler failed\n");
}
/* Enabling the events. */
if (CSL_intcHwControl(hTest,CSL_INTC_CMD_EVTENABLE, NULL) != CSL_SOK)
{
printf("Error: GEM-INTC CSL_INTC_CMD_EVTENABLE command failed\n");
}
#endif
#if 0
handleCIC0 = InitializeCPINTC(0); //initialize cpintc0
if (handleCIC0 == 0)
{
printf ("Error: Unable to open CPINTC0\n");
}
#endif
#if 1
eventId = CpIntc_getEventId(CIC_HOST_INTERRUPT4UART);
Hwi_Params_init(¶ms);
//params.arg = CIC_HOST_INTERRUPT4UART;
params.arg = 1;
params.eventId = eventId;
params.enableInt = TRUE;
// Hwi_create(INTC_INTERRUPT4UART, (ti_sysbios_interfaces_IHwi_FuncPtr)uart_isr, ¶ms, &eb1);
//Hwi_create(INTC_INTERRUPT4UART, &CpIntc_dispatch, ¶ms, &eb1);
Hwi_create(INTC_INTERRUPT4UART, &uart_isr, ¶ms, &eb1);
if (Error_check(&eb1)) {
System_printf("Hwi_create() failed!\n");
}
// Hwi_enableInterrupt(INTC_INTERRUPT4UART);
#endif
#if 1
CpIntc_mapSysIntToHostInt(0, SYSTEM_INTERRUPT_UART_A, CIC_HOST_INTERRUPT4UART);
// CpIntc_dispatchPlug(SYSTEM_INTERRUPT_UART_A, &dummy_isr, SYSTEM_INTERRUPT_UART_A, TRUE);
//CpIntc_dispatchPlug(SYSTEM_INTERRUPT_UART_A,uart_isr, SYSTEM_INTERRUPT_UART_A, TRUE);
CpIntc_dispatchPlug(SYSTEM_INTERRUPT_UART_A,uart_isr, SYSTEM_INTERRUPT_UART_A, TRUE);
CpIntc_enableHostInt(0, CIC_HOST_INTERRUPT4UART);
/* Enable the System Interrupt 20131201 */
CpIntc_enableSysInt(0, SYSTEM_INTERRUPT_UART_A);
#endif
} // Setup_UART_Interrupt
Void main()
{
Task_Handle task;
Error_Block eb;
Setup_UART_Interrupt();
UartInit_self();
//UartSetBaudRate_self(9600);
// platform_uart_set_baudrate(9600);
//Setup_UART_Interrupt();
// Hwi_enable();
Error_init(&eb);
task = Task_create(taskFxn, NULL, &eb);
if (task == NULL) {
System_printf("Task_create() failed!\n");
BIOS_exit(0);
}
BIOS_start(); /* enable interrupts and start SYS/BIOS */
}
int UartTest()
{
int8_t message[] = "\r\n123456789012345678901234567890123456789012345678901234567890\r\n";
int length = strlen((char *)message);
UART_Output(message, length);
return(0);
}