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To slow down SRIO transmission on C6678

Luke Williams
Prodigy 110 points

Hi,

In my hardware, the signal path from the C6678 DSP traverses 2 FPGAs to connect to a DDR3 memory. The DSP is connected to the nearest FGPA by 1-4x port SRIO connection, each lane at 3.125Gbps. It is a design requirement to restrict the uplink DSP transmit bandwidth to the DDR3 to 150MB/sec. I have about 2MB of data to transmit in 16.67msec intervals. What are my options in throttling the uplink DSP transmit data to lower bandwidth?

-          Loading the LSU for 1MB transfers does not give me control to pace the transmit data transfers.

-          Loading the LSU to transmit smaller sizes of data (4KB or 8KB packets) and adding a pacing delay in between engages the CPU too much and will be a waste of computing resource.

-          To use the EDMA with interrupt pacing to do the SRIO transfers is a possible solution.

 

Two questions:

1. Is there any in built functionality within the SRIO peripheral for the transmission of paced data transfers?

2. Are there any EDMA library level support functions for C6678 (similar to the DIO libraries for C6472) to program EDMA to control the SRIO transfers with interrupt pacing?

Thanks.
Luke
  • 0
    TI__Mastermind 23525 points

    Luke,

    Is the 150MB/s limit tied to the data rate 3.125Gbps?  Since your throughput requirement is fairly low, you could possibly lower the data rate to 2.5Gbps or 1.25Gbps, which with a 4X port would give you plenty of bandwidth.  I was going to suggest the smaller packet sizes as the alternative option, with the shadow registers, the CPU overhead to program the LSU would go up but wouldn't seem to be outrageous.  EDMA is a good choice as you mentioned too.  The other question I have is does the FPGA use receiver based flow-control?  If so, it should send RETRY control symbols to the DSP when buffering resources are full.  This mechanism should work fine with no packet loss, but again, I'm not sure exactly where the 150MB/s limit comes from.  Here are my answers to your questions:

    1) The only one I can think of is that the LSU can only track 16 outstanding non-posted packets at a time.  So, if you use NWrite_R packets instead, once you send 16 requests, it won't send the 17th until at least one NWrite_R response packet was received back for the earlier requests.  This will create throttling.  Other than that, the SRIO will send things out as fast as possible.  

    2) No, we don't have DIOLib or equivalent for C66x.  With the LSU expanded capabilities for 1MB tranfers and multiple shadow registers, the EDMA becomes less useful.

    Regards,
    Travis