Call EDMA3 completion ISR on C6657

Norbert Rensing

Hello,

I want to trigger an Interrupt Service Routine by EDMA Interrupt when my EDMA transfer is finished.
I use a TMDXEVM6657 Eva-Board. I want to use only CSL, but no LLD or something like that.

The EDMA configuration works so far, I see that CPINTCRegs.ENA_STATUS_REG[0] is set to 0x00400000, which means that Bit CSL_INTC0_CPU_3_2_EDMACC_GINT=22 is set.
I mapped this System interrupt 22 to CIC's Channel 7, so the Secondary Event (7+20)=27 should be sent to INTC of Core 0.
For INTC, I connected Event 27 to CPU Vector 5 and to my ISR void edmaIsr(void* handle).
Unfortunately I never reach the Breakpoint in my ISR.

-What is wrong with my code or with my understanding of the C6657?
-Do I really need to use the CIC? I only have very few interrupts in my system, so I don't really need the complex routing features.

Thanks,
Norbert

#define CSL_INTC0_CPU_3_2_EDMACC_GINT_CIC0_OUT_X 7u
#define CSL_INTC0_CPU_3_2_EDMACC_GINT_CIC0_OUT_X_CORE0(x) ((x)+20u)
CSL_IntcContext m_context;
CSL_IntcEventHandlerRecord m_EventHandler[2];

void initEdmaInt(void)
{
   /*
   EDMA TCC ==>
   ==> CSL_INTC0_CPU_3_2_EDMACC_GINT=22
   ==> CSL_INTC0_CPU_3_2_EDMACC_GINT_CIC0_OUT_X=7
   ==> //(HINT_MAP[7/4u]>>(7%4u))&0xFu)=7
   ==> CSL_INTC0_CPU_3_2_EDMACC_GINT_CIC0_OUT_X_CORE0(7)=CIC0_OUT(7+20*0)=27
   ==> CSL_INTC_VECTID_5=5
   */
   CSL_IntcObj          intcObjEdma;
   CSL_IntcEventId      eventId = CSL_INTC0_CPU_3_2_EDMACC_GINT;
   CSL_IntcParam        param = CSL_INTC_VECTID_5;
   CSL_CPINTCChannel    channel = CSL_INTC0_CPU_3_2_EDMACC_GINT_CIC0_OUT_X;
   uint32_t               primEvt = CSL_INTC0_CPU_3_2_EDMACC_GINT_CIC0_OUT_X_CORE0(channel);
   CSL_Status           intStat;
   CSL_IntcGlobalEnableState state;

   CSL_IntcEventHandlerRecord EventRecord;

   CSL_IntcHandle hIntcEdma;
   CSL_CPINTC_Handle hCpIntcEdma;

   m_context.numEvtEntries = _COUNT_OF(m_EventHandler);
   m_context.eventhandlerRecord = m_EventHandler;

   intStat = CSL_intcInit(&m_context);

   intStat = CSL_intcGlobalNmiEnable();
   intStat = CSL_intcGlobalEnable(&state);

   hIntcEdma = CSL_intcOpen (&intcObjEdma, primEvt, &param, &intStat);

   EventRecord.handler = &edmaIsr;
   EventRecord.arg = NULL;

   intStat = CSL_intcPlugEventHandler(hIntcEdma, &EventRecord);
   intStat = CSL_intcHwControl(hIntcEdma,CSL_INTC_CMD_EVTENABLE,NULL);

   hCpIntcEdma = CSL_CPINTC_open (CSL_CP_INTC_0);   /* Use CIC0 )assigned to CPU 0..3) */
   /* Disable all host interrupts. */
   CSL_CPINTC_disableAllHostInterrupt(hCpIntcEdma);

   /* Configure no nesting support in the CPINTC Module. */
   CSL_CPINTC_setNestingMode (hCpIntcEdma, CPINTC_NO_NESTING);
   CSL_CPINTC_mapSystemIntrToChannel (hCpIntcEdma, eventId , channel);
   //CSL_CPINTC_mapChannelToHostInterrupt(channel,channel);   //Fixed mapping

   /* Enable system interrupts eventId */
   CSL_CPINTC_enableSysInterrupt (hCpIntcEdma, eventId);

   /* Enable Host interrupt CSL_GEM_CPU_3_2_EDMACC_AETEVT_HOSTINT */
   CSL_CPINTC_enableHostInterrupt (hCpIntcEdma, channel);

   /* Enable all host interrupts also. */
   CSL_CPINTC_enableAllHostInterrupt(hCpIntcEdma);
}

void edmaIsr(void* handle)
{
//...
}

over 11 years ago

0 Xiaohui Li over 11 years ago

TI__Intellectual 1870 points

Hi Norbert,

I never used C6657. But I did some study and here are my comments.

1) According to C6655/57 System Event Mapping Table (SPRS814A, Table 7-33), the system event 27 corresponds to CIC0_OUT(5+20*n). For core0, it corresponds to CIC0_OUT(5). So you need to map whatever the CIC0 interrupt input event you wish to use to CIC0(5). So you need to do two mappings in order to use system input event 27 for INTC

a) Map CIC0 input event (your EDMA completion event) to CIC0(5)

b) Map system event #27 to CPU interrup

2) Make sure the EDMA settup is correct. You may also want to check the EDMA transfer completion by using polling method for checking..

Xiaohui

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Call EDMA3 completion ISR on C6657