AM3874 DDR3 I/O buffer

Hi Michi,

I am not sure I fully understand your question, but I will try to provide you an answer.

I checked the DM814x/AM387x EVM schematics, and DDRx_DQM signal is connected from the DDR3 controller to the DDR3 memory banks through 22E resistor. And DQS/DSQn signals are paired (differential pair) and connected from the DDR3 controller to the DDR3 memory banks through 0E resistors:

Best regards,
Pavel

Please see the datasheet section 8.13 for detailed DDR schematic and routing requirements.

BR,

Steve

Dear Steve-san,

Thank you for your reply.

I would like to know the internal logic of AM3874, not DDR schematic and routing.

Could you supply its information to me?

Best regards,

Michi

Michi,

Michi Yama said:

I would like to know the internal logic of AM3874

Why you need this info? My personal opinion is that TI can not expose such design details over public forums.

Best regards,
Pavel

Why do you need this? What is the actual problem you are trying to solve?

BR,

Steve

Steve-san,

Thank you for your cooperation.

Actually, this is my customer's request. And this is not trouble.

My customer is developing AM3874 system now. And DDR3 memory is used in their system.

Then my customer purchased some measurement equipment recently. They would like to evaluate whether its equipment is used for DDR3 measurement, or not. Of course, they use IBIS model. But it seems to be not enough information. In this reason, they asked me the I/O buffer logic.

Best regards,

Michi

I think the customer needs to get some training from the equipment manufacturer since knowledge of the buffer structure is of absolutely no use when taking measurements.

TI does not disclose the internal buffer structures and they are not necessarily simple architectures as shown in the simplified diagram above.

The question still comes down to "What is the customer actually trying to do?"

BR,

Steve