AM335x U-Boot: no nand device found. Custom board.

When U-Boot boots:
- CS=1 for a long time, CSn=0 for 500ns, CS=1 forever.
- WAIT0 goes low for the same time, but its rise time is higher
- AD0=1 for 2.1us

R/B#, CE# and WP# have 10K external pull-up.

static struct module_pin_mux nand_pin_mux[] = {
 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
 {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
 {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND WAIT */
 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) }, /* NAND_CS0 */
 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) }, /* NAND_ADV_ALE */
 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN) }, /* NAND_OE */
 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN) }, /* NAND_WEN */
 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN) }, /* NAND_BE_CLE */
 {-1},
};

Hi,

FordFairlane said:

Which files should be modified to config this nand flash?

Please check the U-Boot Board Port Labs, section "Adding NAND Support". You can use the git tree (included in SDK_dir/board-support/board-port-labs) to see which files are modified to add NAND support and what exactly are the modifications.

Best regards,
Miroslav

Thank you Miroslav, but I had already read all this information, it is very simple and it is valid only for TI's EVMs.

I have modified many configs to add support for a new nand flash with new id, bigger pages and blocks, different ECC... and now U-Boot finds my nand flash:

musb-hdrc: ConfigData=0xde (UTMI-8, dyn FIFOs, bulk combine, bulk split, HB-ISO Rx, HB-ISO Tx, SoftConn)
musb-hdrc: MHDRC RTL version 2.0
musb-hdrc: setup fifo_mode 4
musb-hdrc: 28/31 max ep, 16384/16384 memory
USB Peripheral mode controller at 47401000 using PIO, IRQ 0
Using default environment

usb_ether
using musb-hdrc, OUT ep1out IN ep1in STATUS ep2in
MAC bc:6a:29:c6:36:e5
HOST MAC de:ad:be:af:00:00
RNDIS ready
musb-hdrc: peripheral reset irq lost!
high speed config #2: 2 mA, Ethernet Gadget, using RNDIS
USB RNDIS network up!
BOOTP broadcast 1
BOOTP broadcast 2
Using usb_ether device
TFTP from server 192.168.3.1; our IP address is 192.168.3.100
Filename 'u-boot.img'.
Load address: 0x807fffc0
Loading: #################################################################
#################################################################
#################################################################
#################################################################
#################################################################
################################################
250 KiB/s
done
Bytes transferred = 1906556 (1d177c hex)

U-Boot 2013.01.01 (Dec 05 2013 - 17:38:27)

I2C: ready
DRAM: 256 MiB
WARNING: Caches not enabled
LCD: Activado
NAND: 1024 MiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
*** Warning - bad CRC, using default environment

musb-hdrc: ConfigData=0xde (UTMI-8, dyn FIFOs, bulk combine, bulk split, HB-ISO Rx, HB-ISO Tx, SoftConn)
musb-hdrc: MHDRC RTL version 2.0
musb-hdrc: setup fifo_mode 4
musb-hdrc: 28/31 max ep, 16384/16384 memory
USB Peripheral mode controller at 47401000 using PIO, IRQ 0
musb-hdrc: ConfigData=0xde (UTMI-8, dyn FIFOs, bulk combine, bulk split, HB-ISO Rx, HB-ISO Tx, SoftConn)
musb-hdrc: MHDRC RTL version 2.0
musb-hdrc: setup fifo_mode 4
musb-hdrc: 28/31 max ep, 16384/16384 memory
USB Host mode controller at 47401800 using PIO, IRQ 0
Net: <ethaddr> not set. Validating first E-fuse MAC
wait_for_user_access Timeout
(...)
wait_for_user_access Timeout
PHY reset timed out
wait_for_user_access Timeout 
(...)

wait_for_user_access Timeout
cpsw, usb_ether
Hit any key to stop autoboot: 0
Card did not respond to voltage select!
mmc0(part 0) is current device
Card did not respond to voltage select!
Booting from nand ...

NAND read: device 0 offset 0x400000, size 0xc00000
12582912 bytes read: OK
Wrong Image Format for bootm command
ERROR: can't get kernel image!

Now I'm going to continue debugging.

Best regards

I have used that same nand flash as an option on one of my boards as well and in case you haven't already discovered this: due to the 4K page size the ROM Loader will use BCH16 if you wish to boot from NAND.  So you need to make sure whatever method you use to flash MLO to NAND you must due it in BCH16.

Thank you very much, Jarrod. I'm searching for BCH16 and I have found many posts and patches about this, could you please tell me the right and best post or patch to start studying?

I use ti-sdk-am335x-evm-06.00.00.00 (u-boot-2013.01.01-psp06.00.00.00 + linux-3.2.0-psp04.06.00.11)

Thank you

This is the U-Boot patch i used:

http://lists.denx.de/pipermail/u-boot/2013-January/145283.html

Note that BCH16 is NOT enabled by default in the patch.  I made some modifications to it so that i could set the BCH via the config file and what i ended up with was this:

diff -r 317cb2e8bf65 -r 14be309e11f8 arch/arm/include/asm/arch-am33xx/cpu.h
--- a/arch/arm/include/asm/arch-am33xx/cpu.h	Tue Dec 10 10:08:26 2013 -0500
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h	Tue Dec 10 10:26:54 2013 -0500
@@ -83,6 +83,10 @@
 	u32 bch_result_x[4];
 };
 
+struct bch_res_4_6 {
+	u32 bch_result_x[3];
+};
+
 struct gpmc {
 	u8 res1[0x10];
 	u32 sysconfig;		/* 0x10 */
@@ -112,7 +116,9 @@
 	u8 res7[12];		/* 0x224 */
 	u32 testmomde_ctrl;	/* 0x230 */
 	u8 res8[12];		/* 0x234 */
-	struct bch_res_0_3 bch_result_0_3[2];	/* 0x240 */
+	struct bch_res_0_3 bch_result_0_3;	/* 0x240 */
+	u32 dummy[44];		/* not used */
+	struct bch_res_4_6 bch_result_4_6;	/* 300 */
 };
 
 /* Used for board specific gpmc initialization */
diff -r 317cb2e8bf65 -r 14be309e11f8 arch/arm/include/asm/arch-am33xx/omap_gpmc.h
--- a/arch/arm/include/asm/arch-am33xx/omap_gpmc.h	Tue Dec 10 10:08:26 2013 -0500
+++ b/arch/arm/include/asm/arch-am33xx/omap_gpmc.h	Tue Dec 10 10:26:54 2013 -0500
@@ -117,4 +117,47 @@
 		{.offset = 106,\
 		 .length = 8 } } \
 }
+
+#define GPMC_NAND_4K_HW_BCH8_ECC_LAYOUT {\
+	.eccbytes = 112,\
+	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
+				16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
+				28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
+				40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
+				52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,\
+				64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,\
+				76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\
+				88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,\
+				100, 101, 102, 103, 104, 105, 106, 107, 108, 109,\
+				110, 111, 112, 113},\
+	.oobfree = {\
+		{.offset = 114,\
+		 .length = 110 } } \
+}
+
+#define GPMC_NAND_4K_HW_BCH16_ECC_LAYOUT {\
+	.eccbytes = 208,\
+	.eccpos = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
+				16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
+				28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
+				40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
+				52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,\
+				64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,\
+				76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\
+				88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,\
+				100, 101, 102, 103, 104, 105, 106, 107, 108, 109,\
+				110, 111, 112, 113, 114, 115, 116, 117, 118, 119,\
+				120, 121, 122, 123, 124, 125, 126, 127, 128, 129,\
+				130, 131, 132, 133, 134, 135, 136, 137, 138, 139,\
+				140, 141, 142, 143, 144, 145, 146, 147, 148, 149,\
+				150, 151, 152, 153, 154, 155, 156, 157, 158, 159,\
+				160, 161, 162, 163, 164, 165, 166, 167, 168, 169,\
+				170, 171, 172, 173, 174, 175, 176, 177, 178, 179,\
+				180, 181, 182, 183, 184, 185, 186, 187, 188, 189,\
+				190, 191, 192, 193, 194, 195, 196, 197, 198, 199,\
+				200, 201, 202, 203, 204, 205, 206, 207, 208, 209},\
+	.oobfree = {\
+		{.offset = 210,\
+		 .length = 14 } } \
+}
 #endif /* __ASM_ARCH_OMAP_GPMC_H */
diff -r 317cb2e8bf65 -r 14be309e11f8 drivers/mtd/nand/omap_gpmc.c
--- a/drivers/mtd/nand/omap_gpmc.c	Tue Dec 10 10:08:26 2013 -0500
+++ b/drivers/mtd/nand/omap_gpmc.c	Tue Dec 10 10:26:54 2013 -0500
@@ -76,8 +76,8 @@
 
 /*
  * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in
- *                   GPMC controller
- * @mtd:        MTD device structure
+ *					 GPMC controller
+ * @mtd:		MTD device structure
  *
  */
 static void __maybe_unused omap_hwecc_init(struct nand_chip *chip)
@@ -170,19 +170,19 @@
 }
 
 /*
- *  omap_calculate_ecc - Generate non-inverted ECC bytes.
+ *	omap_calculate_ecc - Generate non-inverted ECC bytes.
  *
- *  Using noninverted ECC can be considered ugly since writing a blank
- *  page ie. padding will clear the ECC bytes. This is no problem as
- *  long nobody is trying to write data on the seemingly unused page.
- *  Reading an erased page will produce an ECC mismatch between
- *  generated and read ECC bytes that has to be dealt with separately.
- *  E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
- *  is used, the result of read will be 0x0 while the ECC offsets of the
- *  spare area will be 0xFF which will result in an ECC mismatch.
- *  @mtd:	MTD structure
- *  @dat:	unused
- *  @ecc_code:	ecc_code buffer
+ *	Using noninverted ECC can be considered ugly since writing a blank
+ *	page ie. padding will clear the ECC bytes. This is no problem as
+ *	long nobody is trying to write data on the seemingly unused page.
+ *	Reading an erased page will produce an ECC mismatch between
+ *	generated and read ECC bytes that has to be dealt with separately.
+ *	E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
+ *	is used, the result of read will be 0x0 while the ECC offsets of the
+ *	spare area will be 0xFF which will result in an ECC mismatch.
+ *	@mtd:	MTD structure
+ *	@dat:	unused
+ *	@ecc_code:	ecc_code buffer
  */
 static int __maybe_unused omap_calculate_ecc(struct mtd_info *mtd,
 		const uint8_t *dat, uint8_t *ecc_code)
@@ -207,8 +207,8 @@
 
 /*
  * omap_enable_ecc - This function enables the hardware ecc functionality
- * @mtd:        MTD device structure
- * @mode:       Read/Write mode
+ * @mtd:		MTD device structure
+ * @mode:		Read/Write mode
  */
 static void __maybe_unused omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
 {
@@ -258,12 +258,22 @@
 #define ECC_BCH8_NIBBLES	26
 #define ECC_BCH16_NIBBLES	52
 
-static struct nand_ecclayout hw_bch8_nand_oob = GPMC_NAND_HW_BCH8_ECC_LAYOUT;
+#if defined(CONFIG_USE_BCH16_ECC)
+static struct nand_ecclayout nand_ecclayout = GPMC_NAND_4K_HW_BCH16_ECC_LAYOUT;
+#else
+static struct nand_ecclayout nand_ecclayout = GPMC_NAND_4K_HW_BCH8_ECC_LAYOUT;
+//static struct nand_ecclayout nand_ecclayout = GPMC_NAND_HW_BCH8_ECC_LAYOUT;
+#endif
 
 static struct nand_bch_priv bch_priv = {
 	.mode = NAND_ECC_HW_BCH,
+#if defined(CONFIG_USE_BCH16_ECC)
+ 	.type = ECC_BCH16,
+ 	.nibbles = ECC_BCH16_NIBBLES
+#else
 	.type = ECC_BCH8,
 	.nibbles = ECC_BCH8_NIBBLES
+#endif
 };
 
 /*
@@ -280,21 +290,21 @@
 	int8_t i = 0, j;
 
 	if (big_endian) {
-		ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
+		ptr = &gpmc_cfg->bch_result_0_3.bch_result_x[3];
 		ecc_code[i++] = readl(ptr) & 0xFF;
 		ptr--;
 		for (j = 0; j < 3; j++) {
 			ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
 			ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
-			ecc_code[i++] = (readl(ptr) >>  8) & 0xFF;
+			ecc_code[i++] = (readl(ptr) >>	8) & 0xFF;
 			ecc_code[i++] = readl(ptr) & 0xFF;
 			ptr--;
 		}
 	} else {
-		ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[0];
+		ptr = &gpmc_cfg->bch_result_0_3.bch_result_x[0];
 		for (j = 0; j < 3; j++) {
 			ecc_code[i++] = readl(ptr) & 0xFF;
-			ecc_code[i++] = (readl(ptr) >>  8) & 0xFF;
+			ecc_code[i++] = (readl(ptr) >>	8) & 0xFF;
 			ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
 			ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
 			ptr++;
@@ -304,6 +314,53 @@
 	}
 }
 
+static void omap_read_bch16_result(struct mtd_info *mtd, uint8_t big_endian,
+				uint8_t *ecc_code)
+{
+	uint32_t *ptr;
+	int8_t i = 0, j;
+	uint32_t data;
+
+	if(big_endian) {
+		ptr = &gpmc_cfg->bch_result_4_6.bch_result_x[2];
+
+		for (j = 0; j < 7; j++) {
+			if(j == 3) {
+				ptr = &gpmc_cfg->bch_result_0_3.bch_result_x[3];
+			}
+
+			data = readl(ptr);
+			ptr--;
+
+			if(i > 0) {
+				ecc_code[i++] = (data >> 24) & 0xFF;
+				ecc_code[i++] = (data >> 16) & 0xFF;
+			}
+			ecc_code[i++] = (data >> 8) & 0xFF;
+			ecc_code[i++] = data & 0xFF;
+		}
+		ecc_code[i++] = 0;
+		ecc_code[i++] = 0;
+	}
+	else {
+		ptr = &gpmc_cfg->bch_result_0_3.bch_result_x[0];
+
+		for (j = 0; j < 7; j++) {
+			if(j == 4) {
+				ptr = &gpmc_cfg->bch_result_4_6.bch_result_x[0];
+			}
+
+			data = readl(ptr);
+			ptr++;
+
+			ecc_code[i++] = data & 0xFF;
+			ecc_code[i++] = (data >> 8) & 0xFF;
+			ecc_code[i++] = (data >> 16) & 0xFF;
+			ecc_code[i++] = (data >> 24) & 0xFF;
+		}
+	}
+}
+
 /*
  * omap_ecc_disable - Disable H/W ECC calculation
  *
@@ -330,7 +387,7 @@
 	struct nand_chip *chip = mtd->priv;
 	struct nand_bch_priv *bch = chip->priv;
 	uint8_t n_bytes = 0;
-	int8_t i, j;
+	int8_t i;
 
 	switch (bch->type) {
 	case ECC_BCH4:
@@ -338,7 +395,12 @@
 		break;
 
 	case ECC_BCH16:
-		n_bytes = 28;
+		n_bytes = 26;
+
+		/* Last 2 register of ELM need to be zero */
+		syndrome[26] = 0;
+		syndrome[27] = 0;
+
 		break;
 
 	case ECC_BCH8:
@@ -347,16 +409,17 @@
 		break;
 	}
 
-	for (i = 0, j = (n_bytes-1); i < n_bytes; i++, j--)
-		syndrome[i] =  calc_ecc[j];
+	for (i = 0; i < n_bytes; i++) {
+		syndrome[i] = calc_ecc[(n_bytes-1)-i];
+	}
 }
 
 /*
- *  omap_calculate_ecc_bch - Read BCH ECC result
+ *	omap_calculate_ecc_bch - Read BCH ECC result
  *
- *  @mtd:	MTD structure
- *  @dat:	unused
- *  @ecc_code:	ecc_code buffer
+ *	@mtd:	MTD structure
+ *	@dat:	unused
+ *	@ecc_code:	ecc_code buffer
  */
 static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
 				uint8_t *ecc_code)
@@ -368,7 +431,9 @@
 
 	if (bch->type == ECC_BCH8)
 		omap_read_bch8_result(mtd, big_endian, ecc_code);
-	else /* BCH4 and BCH16 currently not supported */
+	else if(bch->type == ECC_BCH16)
+		omap_read_bch16_result(mtd, big_endian, ecc_code);
+	else /* BCH4 currently not supported */
 		ret = -1;
 
 	/*
@@ -434,7 +499,7 @@
 	struct nand_bch_priv *bch = chip->priv;
 	uint8_t syndrome[28];
 	uint32_t error_count = 0;
-	uint32_t error_loc[8];
+	uint32_t error_loc[16];
 	uint32_t i, ecc_flag;
 
 	ecc_flag = 0;
@@ -470,7 +535,7 @@
 /*
  * omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in
  *				GPMC controller
- * @mtd:       MTD device structure
+ * @mtd:	   MTD device structure
  * @mode:	Read/Write mode
  */
 static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode)
@@ -525,8 +590,8 @@
 
 /*
  * omap_enable_ecc_bch- This function enables the bch h/w ecc functionality
- * @mtd:        MTD device structure
- * @mode:       Read/Write mode
+ * @mtd:		MTD device structure
+ * @mode:		Read/Write mode
  *
  */
 static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode)
@@ -611,12 +676,13 @@
  */
 void omap_nand_switch_ecc(int32_t hardware)
 {
+#ifndef CONFIG_AM33XX
 	struct nand_chip *nand;
 	struct mtd_info *mtd;
 
 	if (nand_curr_device < 0 ||
-	    nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
-	    !nand_info[nand_curr_device].name) {
+		nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
+		!nand_info[nand_curr_device].name) {
 		printf("Error: Can't switch ecc, no devices available\n");
 		return;
 	}
@@ -646,19 +712,6 @@
 		nand->ecc.calculate = omap_calculate_ecc;
 		omap_hwecc_init(nand);
 		printf("HW ECC selected\n");
-#ifdef CONFIG_AM33XX
-	} else if (hardware == 2) {
-		nand->ecc.mode = NAND_ECC_HW;
-		nand->ecc.layout = &hw_bch8_nand_oob;
-		nand->ecc.size = 512;
-		nand->ecc.bytes = 14;
-		nand->ecc.read_page = omap_read_page_bch;
-		nand->ecc.hwctl = omap_enable_ecc_bch;
-		nand->ecc.correct = omap_correct_data_bch;
-		nand->ecc.calculate = omap_calculate_ecc_bch;
-		omap_hwecc_init_bch(nand, NAND_ECC_READ);
-		printf("HW BCH8 selected\n");
-#endif
 	} else {
 		nand->ecc.mode = NAND_ECC_SOFT;
 		/* Use mtd default settings */
@@ -671,6 +724,7 @@
 	nand_scan_tail(mtd);
 
 	nand->options &= ~NAND_OWN_BUFFERS;
+#endif
 }
 #endif /* CONFIG_SPL_BUILD */
 
@@ -684,10 +738,10 @@
  * - ecc.hwctl: function to enable (reset) hardware ecc generator
  * - ecc.mode: mode of ecc, see defines
  * - chip_delay: chip dependent delay for transfering data from array to
- *   read regs (tR)
+ *	 read regs (tR)
  * - options: various chip options. They can partly be set to inform
- *   nand_scan about special functionality. See the defines for further
- *   explanation
+ *	 nand_scan about special functionality. See the defines for further
+ *	 explanation
  */
 int board_nand_init(struct nand_chip *nand)
 {
@@ -742,7 +796,7 @@
 	/* Default ECC mode */
 #ifdef CONFIG_AM33XX
 	nand->ecc.mode = NAND_ECC_HW;
-	nand->ecc.layout = &hw_bch8_nand_oob;
+	nand->ecc.layout = &nand_ecclayout;
 	nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
 	nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
 	nand->ecc.hwctl = omap_enable_ecc_bch;
diff -r 317cb2e8bf65 -r 14be309e11f8 include/linux/mtd/mtd-abi.h
--- a/include/linux/mtd/mtd-abi.h	Tue Dec 10 10:08:26 2013 -0500
+++ b/include/linux/mtd/mtd-abi.h	Tue Dec 10 10:26:54 2013 -0500
@@ -125,7 +125,7 @@
  */
 struct nand_ecclayout {
 	uint32_t eccbytes;
-	uint32_t eccpos[128];
+	uint32_t eccpos[208];
 	uint32_t oobavail;
 	struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
 };

Then in your config file if you #define CONFIG_USE_BCH16_ECC along with your other NAND settings then it will enable BCH16.

As for the Kernel i have NOT gotten BCH16 completely working yet.  I was using the patch set by Pekon from: http://arago-project.org/git/projects/?p=linux-omap3.git;a=summary

They are from a different tree so i had to manually apply them to the correct place as files and such do not line up, i can send you my patch so far if you want, but currently i am having issues with it and UBI.  Everything is great for the first read and boot, but on the second boot i get all kinds of ecc errors trying to read ec headers, but all the data is still fine and i can still boot to my nand rootfs just fine.  My priorities kind of got switched up so i just left that branch hanging for now and will come back to it later.  

Until i have time to revisit the issue i am working around it by writing SPL, U-Boot, and the Kernel in BCH16 and writing the rootfs in BCH8.  This allows the ROM code to load up the SPL and avoids any UBI errors in the kernel when reading/writing the rootfs; although i don't know if BCH8 is sufficient especially on the board i have MLC NAND on.  I hope to revisit the code in the future so i can switch completely to BCH16 but if not i may end up going with a smaller page size NAND as i am currently overkilling my space requirements to accommodate for the unknown future.

It also might help to know my setup of how i flash to nand.  Basically factory programming is done simply by inserting a micro SD card.  My board boots to NAND first then mmc0, so on first boot it will fall to the micro SD which will have mlo, u-boot, kernel, rootfs.  U-boot from the SD will then flash MLO and a BCH8 version of itself to NAND.  

It will then reboot itself causing a boot from NAND, ROM will be able to read it because it was flashed as BCH16.  The NAND U-boot is setup as BCH8, and when it first boots it will see there is not kernel or rootfs and will flash these as BCH8 to the NAND.  Then everything is good to go : ).

I hope to get to all BCH16 in the future though : ).

Thank you very much, Jarrod

Now my custom board boots SPL from nand flash but does not boot u-boot, MLO does not jump to u-Boot.

First SPL (/am335x_evm_uart_usbspl/spl/u-boot-spl.bin) is sent over UART0, then ./am335x_evm/u-boot.img is sent over tftp - Ethernet - USB CDC/RNDIS.

musb-hdrc: ConfigData=0xde (UTMI-8, dyn FIFOs, bulk combine, bulk split, HB-ISO Rx, HB-ISO Tx, SoftConn)
musb-hdrc: MHDRC RTL version 2.0 
musb-hdrc: setup fifo_mode 4
musb-hdrc: 28/31 max ep, 16384/16384 memory
USB Peripheral mode controller at 47401000 using PIO, IRQ 0
DEBUG: boot device - 65 ******************************
Using default environment
usb_ether
using musb-hdrc, OUT ep1out IN ep1in STATUS ep2in
MAC bc:6a:29:c6:36:e5
HOST MAC de:ad:be:af:00:00
RNDIS ready
musb-hdrc: peripheral reset irq lost!
high speed config #2: 2 mA, Ethernet Gadget, using RNDIS
USB RNDIS network up!
BOOTP broadcast 1
BOOTP broadcast 2
Using usb_ether device
TFTP from server 192.168.3.1; our IP address is 192.168.3.100
Filename 'u-boot.img'.
Load address: 0x807fffc0
Loading: #################################################################
 #################################################################
 #################################################################
 #################################################################
 #################################################################
 ####################################
 250 KiB/s
done
Bytes transferred = 1845084 (1c275c hex)
DEBUG: Jumping to U-Boot, spl_image: 0x800004a4 ******************************
DEBUG: .name U-Boot 2013.01.01 for am335x boa ******************************
DEBUG: .os 0x00000011 ******************************
DEBUG: .load_addr 0x807fffc0 ******************************
DEBUG: .entry_point 0x80800000 ******************************
DEBUG: .size 0x001c275c ******************************
DEBUG: .flags 0x00000000 ******************************
DEBUG: image entry point: 0x80800000 ******************************
DEBUG: image entry point: 0x80800000 ******************************
DEBUG: image boot params: 0x800004B0 ******************************

U-Boot 2013.01.01 (Dec 11 2013 - 17:43:02)
I2C: ready
DRAM: 256 MiB
WARNING: Caches not enabled
LCD: Activado
NAND: 1024 MiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
*** Warning - bad CRC, using default environment
musb-hdrc: ConfigData=0xde (UTMI-8, dyn FIFOs, bulk combine, bulk split, HB-ISO Rx, HB-ISO Tx, SoftConn)
musb-hdrc: MHDRC RTL version 2.0 
musb-hdrc: setup fifo_mode 4
musb-hdrc: 28/31 max ep, 16384/16384 memory
USB Peripheral mode controller at 47401000 using PIO, IRQ 0
Net: usb_ether
Hit any key to stop autoboot: 0 
Card did not respond to voltage select!
mmc0(part 0) is current device
Card did not respond to voltage select!
Booting from nand ...
NAND read: device 0 offset 0x400000, size 0xc00000
 12582912 bytes read: OK
Wrong Image Format for bootm command
ERROR: can't get kernel image!

Afterwards I download ./am335x_evm/MLO and ./am335x_evm/u-boot.img to RAM using u-boot and program it to flash:

U-Boot# setenv serverip 192.168.3.1; setenv ipaddr 192.168.3.100; tftp 0x82000000 MLO; cp.b 0x82000000 0x82080000 0x80000; cp.b 0x82000000 0x82100000 0x80000; cp.b 0x82000000 0x82180000 0x80000; tftp 0x82200000 u-boot.img; nand erase.ch0
using musb-hdrc, OUT ep1out IN ep1in STATUS ep2in
MAC bc:6a:29:c6:36:e5
HOST MAC de:ad:be:af:00:00
RNDIS ready
musb-hdrc: peripheral reset irq lost!
high speed config #2: 2 mA, Ethernet Gadget, using RNDIS
USB RNDIS network up!
Using usb_ether device
TFTP from server 192.168.3.1; our IP address is 192.168.3.100
Filename 'MLO'.
Load address: 0x82000000
Loading: #############
 238.3 KiB/s
done
Bytes transferred = 64195 (fac3 hex)
using musb-hdrc, OUT ep1out IN ep1in STATUS ep2in
MAC bc:6a:29:c6:36:e5
HOST MAC de:ad:be:af:00:00
RNDIS ready
high speed config #2: 2 mA, Ethernet Gadget, using RNDIS
USB RNDIS network up!
Using usb_ether device
TFTP from server 192.168.3.1; our IP address is 192.168.3.100
Filename 'u-boot.img'.
Load address: 0x82200000
Loading: #################################################################
 #################################################################
 #################################################################
 #################################################################
 #################################################################
 ####################################
 249 KiB/s
done
Bytes transferred = 1845084 (1c275c hex)
NAND erase.chip: device 0 whole chip
Erasing at 0x3ff80000 -- 100% complete.
OK
NAND write: device 0 offset 0x0, size 0x380000
 3670016 bytes written: OK

Finally I reset the board and RBL loads MLO from NAND flash:

U-Boot# reset
resetting ...
CCCCCCCC
U-Boot SPL 2013.01.01 (Dec 11 2013 - 17:43:02)
musb-hdrc: ConfigData=0xde (UTMI-8, dyn FIFOs, bulk combine, bulk split, HB-ISO Rx, HB-ISO Tx, SoftConn)
musb-hdrc: MHDRC RTL version 2.0 
musb-hdrc: setup fifo_mode 4
musb-hdrc: 28/31 max ep, 16384/16384 memory
USB Peripheral mode controller at 47401000 using PIO, IRQ 0
DEBUG: boot device - 5 ******************************
DEBUG: spl_nand_load_image start ******************************
DEBUG: spl_nand_load_image end ******************************
DEBUG: Jumping to U-Boot, spl_image: 0x8000049c ******************************
DEBUG: .name ��� ******************************
DEBUG: .os 0x00000011 ******************************
DEBUG: .load_addr 0x807fffc0 ******************************
DEBUG: .entry_point 0x80800000 ******************************
DEBUG: .size 0x001c275c ******************************
DEBUG: .flags 0x00000000 ******************************
DEBUG: image entry point: 0x80800000 ******************************
DEBUG: image entry point: 0x80800000 ******************************
DEBUG: image boot params: 0x800004A8 ******************************

What is wrong?, I hope u-boot should boot after MLO but it does not.

Thank you in advance.

Just looking quickly through the logs you posted i see this:

You load U-boot.img via tftp:

TFTP from server 192.168.3.1; our IP address is 192.168.3.100
Filename 'u-boot.img'.
Load address: 0x82200000
Loading: #################################################################
 #################################################################
 #################################################################
 #################################################################
 #################################################################
 ####################################
 249 KiB/s
done
Bytes transferred = 1845084 (1c275c hex)

Then you write MLOs and u-boot to Nand flash (i am assuming you are writing from 0x82000000):

NAND write: device 0 offset 0x0, size 0x380000
 3670016 bytes written: OK

Looking at the size of u-boot (0x1C275C) + the size of the MLOs(4 blocks = 0x200000) you have 0x3C275C Bytes but your NAND Write is only writing 0x380000 Bytes, meaning you are not writing all of u-boot to NAND.  That would be my first guess as to what the problem is, so try increasing the write amount and see what happens.

Good Luck!!!! : )

Thank you very much, Jarrod, once again.

I had reserved 1.5MB in the nand flash memory map but my current u-boot needs 2MB.

Now MLO and u-boot boot fine from nand flash, but very slowly, only 600KB/s. Today I don't mind the speed but I'll have to improve it in the near future. I have tested a patch for a 40ns flash but it does not work with my custom board, flash memory hangs and u-boot says "no devices available" (nand).

This config boots @600KB/s.

#define M_NAND_GPMC_CONFIG1 0x00000800
#define M_NAND_GPMC_CONFIG2 0x001e1e00
#define M_NAND_GPMC_CONFIG3 0x001e1e00
#define M_NAND_GPMC_CONFIG4 0x16051807
#define M_NAND_GPMC_CONFIG5 0x00151e1e
#define M_NAND_GPMC_CONFIG6 0x16000f80
#define M_NAND_GPMC_CONFIG7 0x00000008

This config does not boot:

#define M_NAND_GPMC_CONFIG1 0x00000800
#define M_NAND_GPMC_CONFIG2 0x00040400
#define M_NAND_GPMC_CONFIG3 0x00040400
#define M_NAND_GPMC_CONFIG4 0x03010301
#define M_NAND_GPMC_CONFIG5 0x00040404
#define M_NAND_GPMC_CONFIG6 0x04000689

Best regards

I am glad u were able to get it working!!! : )

I did notice things were a little bit slower, due to the increase in page sizes but i did not change any of the defaults settings.  For the most part things still seem acceptably quick, the only real slow process is that of writing my 40MB root file system to NAND.

The default KERNEL timings (as set in the board-am335x.c file) i also did not have to change to work with this NAND flash.  However, i did need to up the timings in the Kernel for my MLC NAND (MT29F16G08CBACAWP).  The MLC worked fine with the U-Boot default settings as they are alot slower than the kernels, but i had to really up the timings in the Kernel.  Anyways maybe you could start with the original am335x Kernel timings as a starting point?

static struct gpmc_timings am335x_nand_timings = {
	.sync_clk = 0,

	.cs_on = 0,
	.cs_rd_off = 44,
	.cs_wr_off = 44,

	.adv_on = 6,
	.adv_rd_off = 34,
	.adv_wr_off = 44,
	.we_off = 40,
	.oe_off = 54,

	.access = 64,
	.rd_cycle = 82,
	.wr_cycle = 82,

	.wr_access = 40,
	.wr_data_mux_bus = 0,
};

I Believe those settings should translate to:

#define M_NAND_GPMC_CONFIG1	0x00000800
#define M_NAND_GPMC_CONFIG2	0x00050500
#define M_NAND_GPMC_CONFIG3	0x00050401
#define M_NAND_GPMC_CONFIG4	0x04010601
#define M_NAND_GPMC_CONFIG5	0x00070909
#define M_NAND_GPMC_CONFIG6	0x04000F80
#define M_NAND_GPMC_CONFIG7	0x00000F48

My speed is sufficient enough for my purposes, but i may do some tuning in the future.  So if you come across some concrete config settings that achieve the best speed while maintaining reliability i would definitely be interested to see them : ).

Hi Ford Fair lane,

I am also using MT29F8G08ABABA nand in my am335x platform. I am unable to boot from my nand by default instead of mmc. 

What are the changes required in u-boot (SDK5/6/7) & kernel(SDK5/6/7) . Could you send me the required changes u-boot & kernel files, It is very easy to replicate the same in my source.

I have tried as per your links, but i could't able to work it.

Please do the needful.

Thanks