About concurrent usage of PCIe between Cores and EDMA

Hello,

We are having some troubles on PCIe traffic in our system and so I have some questions in my mind. 

Just some basic info about PCIe interface of our system: An 6678 DSP is deployed as RC and there is an FPGA at the other end as EP. There is no other EPs in the system. We are using core 0 for managing PCIe dataflow and EDMA for burst data transfers. All DSP transactions are outbound translations.

Here are some scenarios that I want to ask :

1. Scenario:
   1. PCIe is initialized by Core 0. Link is up.
   2. All 8 cores do read&write transactions(not burst) to the EP concurrently without any sychronization mechanism. Each core reads&writes to the different addres of EP.
   3. Actually I did tested this scenario and saw that there is no problem. PCIe peripheral handles concurrency usage among cores. 
   4. Is this observation true?
2. Scenario:
   1. PCIe is initialized by Core 0. Link is up.
   2. EDMA is initialized by Core 0. An EDMA channel is configured to do burst data read from EP.
   3. EDMA channel is triggered. And during burst data transfer, Core 0 tried to do a single data read(or write) from(or to) EP from an address other than the burst read address. 
   4. What happens in this scenario ? Do we have to establish a synchronisation mechanism for this? (such as waiting until the finishing of the EDMA transfer ? )
3. Scenario:
   1. PCIe is initialized by Core 0. 
   2. MSI_0 is also configured. EP will notify DSP through MSI.
   3. Link is up.
   4. EDMA is initialized by Core 0. An EDMA channel is configured to do burst data read from EP.
   5. EDMA channel is triggered. And during burst data transfer, EP tries to send MSI_0.
   6. Actually I observed this scenario. What I saw is EP can't get its interrupt ready signal and later DSP can't get its next MSI_0. And PCIe data flow totally stops. Moreover we loose the debug connection and Core 0 jumps to a meaningless value. I guess something wrong happens in the PCIe protocol and it goes to an undefined state. And this causes debug connection to loose.
   7. What may be the problem in this scenario?
4. Scenario:
   1. PCIe is initialized by Core 0. Link is up.
   2. EDMA is initialized by Core 0. 2 EDMA channels are configured. First one is configured to do burst data read. Second one is configured to do burst data write.
   3. First EDMA channel is triggered. During burst data read, second EDMA channel is triggered.
   4. What happens in this scenario?
   5. Once I observed a similar scenario and it seemed to me that both EDMA channels tried to make burst data transfers concurrently and both channels' data were corrupt. I don't find it logical because EDMA works through some queues. When I trigger both EDMA channels same time, it should transfer data in sequence assuming they are using the same queue. So what may be the problem then?