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how ARM uses shared hardware memory like msmc or ddr

Hi All,

I want to know how ARM uses shared memory like MSMC, DDR like for DSP there is somthing like this is provided by "ti/runtime/resmgr/resmgr.h" which provides structure "ResMgr_ResourceCfg" its fields need to be updated for each core that will cover memory allocation on msmc and ddr etc.

Is there any example\document in support of this?

Please rply asap.

Thanks & Regards,

Lokesh Khandelwal

  • I would also like to know how ARM uses shared memory like MSMC and DDR. I need to know how ARM uses the shared memory in order to know:

     * What memory locations is it safe to load the DSP ELF image in DDR?
     * What memory locations can I allocate buffers for use with Multicore Navigator queues so that the buffers can be used by both ARM and DSPs?

    It looks like ARM does not touch the MSMC memory after bootup, but how to control the way ARM uses the DDR memory is still unknown to me.

    I'm using the XTCIEVMK2X Rev 2.0

  • I suggest that you read about the mem_reserve in Exploring Chpater and System Management in Developing Chapter of the User's Guide, http://processors.wiki.ti.com/index.php/MCSDK_User_Guide_for_KeyStone_II. I also posted the answer in the other thread that the area is mapped to DDR3A area at Physical address 0x08 0000 0000 where both ARM and DSP can be accessed.

    Rex

  • Hi Rex

    Thanks for the answer, it seems like mem_reserve is the way to go when both ARM and DSP are both seeing DDR3A in the same memory area. It will at least give me a way to hide a portion of DDR3A from ARM so it will be used exclusively by the DSP's.

  • Thanks Rex, In fact, I can access DDR area at physical address 0x6000 0000 both on ARM and DSP, If I add some delay in write or read procedure, I can work. but if I remove delay function call, variable that written from ARM can NOT be got by DSP.