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AM3352 interface with DDR3L routing specification Query

Karthik Puliyadi
Prodigy 160 points
Other Parts Discussed in Thread: AM3352

Hi

I had interface AM3352 with DDR3L IC, where the longest trace of ADD_CNTRL has 33.429mm (nWE).

1. What tolerance should be considered as per datasheet. Whether A1+A2+AS skew(Max 25+25 mil)  or CALM (+/-50 mil).

2. A1+A2 skew is Max 25 mil. What should be Min level need to be consider. 

  • 0
    TI__Guru**** 393215 points
    How many memory chips do you have? Do you have Vtt termination resistors?
  • 0 in reply to Biser Gatchev-XID
    Prodigy 160 points

    One DDR3L and VTT termination is available

  • 0 in reply to Karthik Puliyadi
    TI__Guru**** 393215 points
    Hi Karthik,
     
    Thanks for the clarification. On your questions:
     
    1. In your case CACLM = A1 + A2 + 300mils. All Address/Control traces length should be within CACLM +/- 50mils. A1 +A2 should be the longest Manhattan length of the Address/Control nets class. This can be seen on almost all CAD systems (sometimes mentioned as unrouted net length). The A1 + A2 skew of 25mils means that all Address/Control trace lengths between the processor and DDR should be within 25mils (if the shortest is 1000mils the longest must be less than 1025mils). For the AS trace (stub from Address/Control trace to DDR pin) max. length is 100mils, max skew is 25mils. For the AT trace (from branch to DDR pin to Vtt resistor) there are no strict requirements - typical length is 500mils, typical skew is 100mils, but the smaller you make these the better.
     
    2. The minimum skew is 0 (perfect case - all traces are equally long).