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C6746 EMIFA Registers not writeable

1768011
Intellectual 600 points

Hi!

C6746 Processor can't access Data on EMIFA.

  • On CS2, on all addresses 0x0631 is read back. A 8MB Nor Flash is connected to this ChipSelect.
  • On CS3, on all addresses 0xFFFF is read back. There's nothing connected to CS5
  • On CS4 a FPGA is connected, on all addresses 0x0000 is read back.
  • The EMIFA configuration registgers display 0x68000010 through 0x6800001C
  • The PSC0 MDSTAT Registers shows 0x00001E03
  • EMIFA is configured to use Sysclock3, PLL should be fine, otherewise the processor would not be working at all? PLL0.PLLSTAT register shows 0x00000006, so i guess that's fine too!

Are there any other possibilities that could shut down the EMIFA? If the EMIFA isn't working at all, why is there data on CS2?

Eventhough i suspect that there's some gone-wild-pointer that accidently modified some configuration register, it would be nice to know which registers can have this effect to simplify debugging.

Thank you!

  • 0
    TI__Guru* 84110 points

    011,

    The symptoms are of an EMIFA that is not properly powered and clocked.

    The easiest way to check this is to try the GEL file that comes with the EVM or downloaded from the TI Wiki Pages (search for C674x and find the GEL file for the 456MHz devices). You can run that GEL or at least the PSC_All_On_Full_EVM() function (or parts of it that apply to your board).

    Do you have a C6748 EVM that you can test some of your code against the GEL?

    Regards,
    RandyP

  • 0
    TI__Mastermind 35645 points

    HI,

    Thanks for your post.

    Please refer the C674x EMIFA user guide to know the details on registers as below:

    http://www.ti.com/lit/ug/sprufl6f/sprufl6f.pdf

    In the above, also refer Appendix A2 for example configurations for SDRAM and flash interface.

    If you use starterware API's, EMIFA supports multiple ECC algorithms, may be you shall refer the below starterware wiki for EMIFA:

    http://processors.wiki.ti.com/index.php/StarterWare_EMIFA#Basic_Read.2FWrite_Access

    Thanks & regards,

    Sivaraj K

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  • 0 in reply to Sivaraj Kuppuraj
    Intellectual 600 points

    Hi RandyP, Hi Sivaraja,

    thank you for your replies!

    After some further investigations i can now supply more details:

    • EMIF is working fine after booting and after initialisation by the DSP Software
    • A device connected to the EMIF on CS4 with 16bit bus width and extended wait activated seems to fail
    • for some reason, probably when doing a double-word access, the EMA_WAIT for this chip select (low-active) goes low and stays there.
    • i now configured the EMIF to generate a event upon a timeout of EMA_WAIT and subsequently jump into an ISR
    • having a breakpoint in the ISR now showsthat the EMIF configuration registers are no longer writeable. All registers show 0x00000000 through jtag

    Following are two redundant questions:

    • Why are the EMIF registers no longer writeable and how can i solve this issue? I can't even turn of EMA_WAIT for that chipselect even if i wanted to.
    • Are there any further actions that need to be done when a EMA_WAIT timeout occurs?

    Thank You!

    -

  • 0 in reply to 1768011
    Intellectual 600 points

    The following makes the registers read and writeable again:

    • put the PowerSleepController0 EMIF Module into "SwRstDisable" state
    • put the EMIF Module into "Enable" etate

    Any other suggestions what's going on / going wrong?

  • 0 in reply to 1768011
    Intellectual 600 points

    Final examination of this issue showed the following:

    One device connected to the EMIFA, a FPGA, requires extended wait. For some reason the FPGA stalled and kept the EMA_WAIT low. In this condition the EMIF-A is blocked until the configured timeout occurs. Fortunately the EMIF can generate an event (55 - EMIFA Interrupt) for interrupt generation if this timeout occurs. If in the ISR the EMIF is reset and configured again, the other peripherals can be accessed again.