TMS320С6678 DDR3 test failed...

Could you please provide more detailed information regarding your problem. What exactly doesn't work? What have you done trying to solve the problem.

1) does not pass the standard test of memory, written in the gel file (ddr3_memory_test ())

2) in recording and reading the RAM, the values ​​do not match

Tried to do different settings, lowering the memory frequency up to 133MHz, exhibited different timings of RAM.
Generally tried many things, but the result is zero.
Supply all present.

Hi Denis,

I don't see any obvious problems with the information that you sent. It sounds like you've done some debug but let me ask some questions. 

1) Have you measured all the power supplies for the part? Are they correct and within tolerance.

2) Are you following the power sequencing requirements, including the delay between the rising edge of PORz and the rising edge of RESETFULLz?

3) Did the bootmode latched correctly?

4) Is the main PLL programming correctly? What is the frequency measured on SYSCLKOUT?

5) What is the frequency of the clock input at DDRCLK?

6) Have you measured the DDRCLKOUT signal? What is the frequency? How does it look?

7) How is the interface routed? What layers are the data lanes routed on? Are they adjacent to a solid ground plane?

8) Are the address/command signals routed in a fly-by manner? What layers are they routed on? Are they adjacent to a solid plane?

9) Is there any pattern to the data that you are reading back? Is the read failing in all bits or just some? If you read repeatedly from the same address do you get the same value or does the value change? 

Regards, Bill

Hi Bill,

1) Power checked, everything is fine

2) power is supplied in the order specified in your documentation (SPRS691TS page 116, 7.2.1.2 IO-Before-Core Power Sequencing)

3) All bootmode  bits = 0, LENDIAN = 1, DDRSLRATE[1:0] = 00

4) Unfortunately SISCLKOUT signal is not routing, but power increases when programmng main PLL

5) input DDRCLK = 66.6667 MHz

6) DDRCLKOUT signal corresponds to the values ​​prescribed in the GEL file
if PLLM_DR = 19, then DDRCLKOUT = 666,67 MHz if PLLM_DR = 11 then DDRCLKOUT = 400 MHz, looks fine from 400 mV to 1200 mV peak to peak.

7,8) data / address / control/clk on 3,5,7,9,11 (2,4,6,8,10,12 -GND plane, 1(top) - 0.75REF, 13 - POWER 1.5), technology routing fly-by

9) are always different data are read, regardless of the fact that previously writed, or one bit is not equal

I use the debugger XDS100.

A detailed study showed that when reading the RAM memory chip does not give signals DQS and DQx, and are attended by a constant level of 0.75 V. When writting signals DQS and DQx range from 400 to 1200 mV

I do not know what to think now...

Hi Denis,

Unfortunately they cannot be changed. The RAS and CAS outputs must be routed to the proper pins on the DDR3 memories.

Regards, Bill