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uPP and L1D cache

Elnur Babishov
Intellectual 895 points

Hello!

I use c6657evm. I want to understand why I must disable L1D cache for uPP? uPP does not work correctly with enabled L1D. Performance of my code decreases without L1D cache. Is where solution of this problem?

  • 0
    TI__Mastermind 20790 points

    Elnur Babishov,

    IDMA support for UPP:
    An internal DMA controller services uPP transfers without consuming system EDMA resources.
    It is recommended to use uPP with its own internal DMA, here all the uPP events are connected to internal DMA channels I/Q.

    Window Address: A pointer to the first data word in the buffer.

    Line Size: The number of bytes per data line.

    Line Count: The number of data lines in the entire transfer.

    Line Offset: The offset address between the start of each data line.

    These parameters allow some flexibility in organizing uPP data buffers.


    Where you find disable L1D cache for uPP?
    Refer the below thread for L1D, this will help you.
    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/283796/994212.aspx#994212

  • 0 in reply to Pubesh
    Intellectual 895 points

    Pubesh,
    Thank you for answer.

    I have to use these strings of code before upp initialization:

        hBootCfg->KICK_REG0 = 0x83e70b13;  // Kick0 register + data(unlock)
        hBootCfg->KICK_REG1 = 0x95a4f1e0;  // Kick1 register + data(unlock)
        // Disable L1D cache
        *(Uint32 *)(0x01840040) &= 0xFFFFFFF0;

    Upp does not work correctly without it.